Input/output buffer circuit for semiconductor integrated circuit

Claim 2

An input/output buffer circuit for a semiconductor integrated circuit, comprising: an input/output pad located in the semiconductor integrated circuit; an input buffer circuit for receiving a first signal through said input/output pad; an output buffer circuit composed of a first MOS field-effect transistor and a second MOS field-effective transistor of first and second conductivity types, respectively, connected in series between first and second supply potential terminals, said output buffer circuit outputting a second signal to an output node between said first and second MOS field-effect transistors in accordance with a third signal supplied from an internal circuit located in the semiconductor integrated circuit; and a third MOS field-effect transistor of the second conductivity type having a lower threshold voltage than that of said first and second MOS field effective transistors and having a first current path connected to said output node, a second current path connected to said input/output pad, and a gate supplied with a potential equal to that of said first potential supply terminal, wherein an input node of said input buffer circuit is connected to the output node of said output buffer circuit.

Claim 3

An input/output buffer circuit for a semiconductor integrated circuit, comprising: an input/output pad located in the semiconductor integrated circuit; an input buffer circuit for receiving a first signal from the outside of the semiconductor integrated circuit through said input/output pad; an output buffer circuit comprising first and second MOS field-effect transistors, respectively, of a first and a second conductivity type connected in series between a first supply potential terminal and a second supply potential terminal, said output buffer circuit outputting a second signal to an output node between said first MOS field-effect transistor and said second MOS field-effect transistor in accordance with a second signal from an internal circuit located in the semiconductor integrated circuit; and a third MOS field-effect transistor of the second conductivity type connected between an output node of said output buffer circuit and said input/output pad, and having a gate supplied with a potential higher than that of said first supply potential terminal, wherein an input node of said input buffer circuit is connected to the output node of said output buffer circuit.

Claim 4

An input/output buffer circuit for a semiconductor integrated circuit, comprising: an input/output pad located in the semiconductor integrated circuit; an input buffer circuit for receiving a first signal from the outside of the semiconductor integrated circuit through said input/output pad; an output buffer circuit comprising first and second MOS field-effect transistors, respectively, of a first and a second conductivity type connected in series between a first supply potential terminal and a second supply potential terminal, said output buffer circuit outputting a second signal to an output node between said first MOS field-effect transistor and said second MOS field-effect transistor in accordance with a second signal from an internal circuit located in the semiconductor integrated circuit; and a third MOS field-effect transistor of the second conductivity type connected between an output node of said output buffer circuit and said input/output pad, and having a gate supplied with a potential higher than that of said first supply potential terminal, wherein an input node of said input buffer circuit is connected to the output node of said output buffer circuit.

Claim 5

The input/output buffer circuit according to claim 2, further comprising a bootstrap circuit for boosting an externally provided supply potential to generate a potential having a level higher than that of the first supply terminal, and for applying the externally provided supply potential to the gate of said third MOS field-effect transistor or to a fourth MOS field-effect transistor of the second conductivity type.

Claim 6

An input/output buffer circuit for a semiconductor integrated circuit, comprising: an input/output pad located in the semiconductor integrated circuit; an input buffer circuit for receiving a first signal from the outside of the semiconductor integrated circuit through said input/output pad; an output buffer circuit having a first MOS field-effect transistor of a first conductivity type and a second MOS field-effect transistor of a second conductivity type, the first and second MOS field effect transistors connected in series between a first supply potential terminal and a second supply potential terminal, said output buffer circuit outputting a second signal to an output node between said first MOS field-effect transistor and said second MOS field-effect transistor in accordance with a signal from an internal circuit located in the semiconductor integrated circuit; a third MOS field-effect transistor of the second conductivity type connected between the output node of said output buffer circuit and said input/output pad; and a fourth MOS field-effect transistor of the second conductivity type connected between said input/output pad and an input node of said input buffer circuit, wherein said third and fourth MOS field-effect transistors are MOS field-effect transistors which have a threshold voltage which is lower than a threshold voltage of said first MOS field-effect transistor and to which a potential is applied having the same level as that applied to the first supply potential terminal.

Claim 7

An input/output buffer circuit for a semiconductor integrated circuit, comprising: an input/output pad located in the semiconductor integrated circuit; an input buffer circuit for receiving a first signal from the outside of the semiconductor integrated circuit through said input/output pad; an output buffer circuit having a first MOS field-effect transistor of a first conductivity type and a second MOS field-effect transistor of a second conductivity type, the first and second MOS field effect transistors connected in series between a first supply potential terminal and a second supply potential terminal, said output buffer circuit outputting a second signal to an output node between said first MOS field-effect transistor and said second MOS field-effect transistor in accordance with a signal from an internal circuit located in the semiconductor integrated circuit; a third MOS field-effect transistor of the second conductivity type connected between the output node of said output buffer circuit and said input/output pad; and a fourth MOS field-effect transistor of the second conductivity type connected between said input/output pad and an input node of said input buffer circuit, wherein said third and fourth MOS field-effect transistors are MOS field-effect transistors which have a threshold voltage which is lower than a threshold voltage of said first MOS field-effect transistor and to which a potential is applied having the same level as that applied to the first supply potential terminal.

Claim 8

The input/output buffer circuit according to claim 4, wherein said fourth MOS field-effect transistor is smaller in size than said third MOS field-effect transistor.

Claim 9

An input/output buffer circuit for a semiconductor integrated circuit, comprising: an input/output pad located in the semiconductor integrated circuit; an input buffer circuit for receiving a first signal from the outside of the semiconductor integrated circuit through said input/output pad; an output buffer circuit having a first MOS field-effect transistor of a first conductivity type and a second MOS field-effect transistor of a second conductivity type the first and second MOS field effect transistors connected in series between a first supply potential terminal and a second supply potential terminal, said output buffer circuit outputting a second signal to an output node between said first MOS field-effect transistor and said second MOS field-effect transistor in accordance with a third signal from an internal circuit located in the semiconductor integrated circuit; a third MOS field-effect transistor of the second conductivity type connected between the output node of said output buffer circuit and said input/output pad; and a fourth MOS field-effect transistor of the second conductivity type connected between said input/output pad and an input node of said input buffer circuit, wherein said third and fourth MOS field-effect transistors have gates to which a potential is applied having a level higher than that of the first supply potential terminal.

Claim 10

An input/output buffer circuit for a semiconductor integrated circuit, comprising: an input/output pad located in the semiconductor integrated circuit; an input buffer circuit for receiving a first signal from the outside of the semiconductor integrated circuit through said input/output pad; an output buffer circuit having a first MOS field-effect transistor of a first conductivity type and a second MOS field-effect transistor of a second conductivity type the first and second MOS field effect transistors connected in series between a first supply potential terminal and a second supply potential terminal, said output buffer circuit outputting a second signal to an output node between said first MOS field-effect transistor and said second MOS field-effect transistor in accordance with a third signal from an internal circuit located in the semiconductor integrated circuit; a third MOS field-effect transistor of the second conductivity type connected between the output node of said output buffer circuit and said input/output pad; and a fourth MOS field-effect transistor of the second conductivity type connected between said input/output pad and an input node of said input buffer circuit, wherein said third and fourth MOS field-effect transistors have gates to which a potential is applied having a level higher than that of the first supply potential terminal.

Claim 11

The input/output buffer circuit according to claim 6, wherein said fourth MOS field-effect transistor is smaller in size than said third MOS field-effect transistor.

Claim 12

The input/output buffer circuit according to claim 6, further comprising a bootstrap circuit for boosting an externally provided supply potential to generate a potential having a level higher than that of the first supply potential terminal, and for applying the potential to the gate of said third MOS field-effect transistor or to the gate of said fourth MOS field-effect transistor.

Claim 13

An input/output buffer circuit for a semiconductor integrated circuit, comprising: an input/output pad located in the semiconductor integrated circuit; an input buffer circuit for receiving a first signal from the outside of the semiconductor integrated circuit through said input/output pad; an output buffer circuit having a first MOS field-effect transistor of a first conductivity type and a second MOS field-effect transistor of a second conductivity type the first and second MOS field-effect transistors connected in series between a first supply potential terminal and a second supply potential terminal, said output buffer circuit outputting a second signal to an output node between said first MOS field-effect transistor and said second MOS field-effect transistor in accordance with a third signal from an internal circuit located in the semiconductor integrated circuit; a third MOS field-effect transistor of the second conductivity type connected between the output node of said output buffer circuit and said input/output pad; and a fourth MOS field-effect transistor of the second conductivity type connected between said input/output pad and an input node of said input buffer circuit, wherein one of said third and fourth MOS field-effect transistors has a threshold voltage lower than a threshold voltage of the first MOS field-effect transistor and to which a potential is applied having the same value as that applied to the first supply potential terminal, and the other of said third and fourth MOS field-effect transistors has a gate to which a potential is applied having a level higher than that of the first supply potential terminal.

Claim 14

An input/output buffer circuit for a semiconductor integrated circuit, comprising: an input/output pad located in the semiconductor integrated circuit; an input buffer circuit for receiving a first signal from the outside of the semiconductor integrated circuit through said input/output pad; an output buffer circuit having a first MOS field-effect transistor of a first conductivity type and a second MOS field-effect transistor of a second conductivity type the first and second MOS field-effect transistors connected in series between a first supply potential terminal and a second supply potential terminal, said output buffer circuit outputting a second signal to an output node between said first MOS field-effect transistor and said second MOS field-effect transistor in accordance with a third signal from an internal circuit located in the semiconductor integrated circuit; a third MOS field-effect transistor of the second conductivity type connected between the output node of said output buffer circuit and said input/output pad; and a fourth MOS field-effect transistor of the second conductivity type connected between said input/output pad and an input node of said input buffer circuit, wherein one of said third and fourth MOS field-effect transistors has a threshold voltage lower than a threshold voltage of the first MOS field-effect transistor and to which a potential is applied having the same value as that applied to the first supply potential terminal, and the other of said third and fourth MOS field-effect transistors has a gate to which a potential is applied having a level higher than that of the first supply potential terminal.

Claim 15

The input/output buffer circuit according to claim 9, wherein a channel width of said fourth MOS field-effect transistor is smaller than a channel width of said third MOS field-effect transistor.

Claim 16

The input/output buffer circuit according to claim 9, further comprising a bootstrap circuit for boosting an externally provided supply potential to generate a potential having a level higher than that of the first supply potential terminal, and for applying the potential to the gate of said third MOS field-effect transistor or to the gate of said fourth MOS field-effect transistor.

Claim 17

The input/output buffer circuit according to claim 1, further comprising a high-resistance element connected between the output node of said output buffer circuit and said second supply potential terminal.

Claim 18

The input/output buffer circuit according to claim 2, further comprising a high-resistance element connected between the output node of said output buffer circuit and said second supply potential terminal.

Claim 19

The input/output buffer circuit according to claim 4, further comprising a high-resistance element connected between the output node of said output buffer circuit and said second supply potential terminal.

Claim 20

The input/output buffer circuit according to claim 6, further comprising a high-resistance element connected between the output node of said output buffer circuit and said second supply potential terminal.

Claim 21

The input/output buffer circuit according to claim 9, further comprising a high-resistance element connected between the output node of said output buffer circuit and said second supply potential terminal.

Claim 22

The input/output buffer circuit according to claim 12, wherein said high-resistance element comprises a fifth MOS field-effect transistor of the second conductivity type.

Claim 23

The input/output buffer circuit according to claim 13, wherein said high-resistance element comprises a fifth MOS field-effect transistor of the second conductivity type.

Claim 24

The input/output buffer circuit according to claim 14, wherein said high-resistance element comprises a fifth MOS field-effect transistor of the second conductivity type.

Claim 25

The input/output buffer circuit according to claim 15, wherein said high-resistance element comprises a fifth MOS field-effect transistor of the second conductivity type.

Claim 26

The input/output buffer circuit according to claim 16, wherein said high-resistance element comprises a fifth MOS field-effect transistor of the second conductivity type.

Claim 27

The input/output buffer circuit according to claim 16, wherein said high-resistance element comprises a fifth MOS field-effect transistor of the second conductivity type.