US4806795A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transfer gate circuit protected from latch up
Assignee: Fujitsu VLSI Ltd
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Filing: 1987-09-16
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Granted: 1989-02-21
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Expires: 2007-09-16
Abstract
Abstract A transfer gate circuit including a first MIS transistor which transmits an input signal supplied from an input side thereof to an output side thereof in accordance with a control signal supplied to a gate of the first MIS transistor; an inverter circuit connected between power supply lines which inverts the potential of the transmitted input signal; and an output level guarantee circuit comprising second and third MIS transistors which have conductivity type opposite to that of the first MIS transistor and are connected in series between one of the power supply lines and the output side, an output signal of the inverter circuit being supplied to a gate of the second MIS transistor, an inverted signal of the control signal supplied to the gate of the first MIS transistor being supplied to a gate of the third MIS transistor.
Inventors
- 👤 Masao Nakano
- 👤 Tsuyoshi Ohira
- 👤 Hidenori Nomura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 23:58
CPC Classifications
H; H04; H04B; H04B14/00; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/687; H03K17/6871; H03K17/6872; H03K17/16
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
184 words
A transfer gate circuit comprising: an inverter circuit connected between power supply lines, said inverter circuit having an input signal input thereto, said inverter circuit inverting a potential of said input signal and outputting said inverted input signal at an output thereof; a first MIS transistor having an input, an output and a gate, said input thereof being connected to an input of said inverter circuit, said first MIS transistor transmitting said input signal from said input thereof to said output thereof according to a control signal supplied to said gate; and an output level guarantee circuit, said output level guarantee circuit including second and third MIS transistors of a conductivity type opposite to said first MIS transistor, said second and third MIS transistors being connected in series between said power supply lines and said output of said first MIS transistor, said output of said inverter circuit being supplied to a gate of said second MIS transistor, and an inverted signal of said control signal, supplied to the gate of said first MIS transistor, being supplied to a gate of said third MIS transistor.
Claim 2
Dependent Claim
184 words
A transfer gate circuit comprising: an inverter circuit connected between power supply lines, said inverter circuit having an input signal input thereto, said inverter circuit inverting a potential of said input signal and outputting said inverted input signal at an output thereof; a first MIS transistor having an input, an output and a gate, said input thereof being connected to an input of said inverter circuit, said first MIS transistor transmitting said input signal from said input thereof to said output thereof according to a control signal supplied to said gate; and an output level guarantee circuit, said output level guarantee circuit including second and third MIS transistors of a conductivity type opposite to said first MIS transistor, said second and third MIS transistors being connected in series between said power supply lines and said output of said first MIS transistor, said output of said inverter circuit being supplied to a gate of said second MIS transistor, and an inverted signal of said control signal, supplied to the gate of said first MIS transistor, being supplied to a gate of said third MIS transistor.
Claim 3
Dependent Claim
65 words
A transfer gate circuit according to claim 1, further comprising another inverter circuit for supplying said control signal to the gate of said first MIS transistor, said another inverter circuit being connected between said power supply lines, said one of power supply lines having high potential level being connected to said another inverter circuit at the connecting point adjacent to that of said inverter circuit.
Claim 4
Dependent Claim
52 words
A transfer gate circuit according to claim 1, wherein said first MIS transistor is an N-channel type transistor, and said second and third MIS transistors are P-channel type transistors connected in series between said one of power supply lines having high potential level and said output side of said first MIS transistor.
Claim 5
Dependent Claim
52 words
A transfer gate circuit according to claim 1, wherein said first MIS transistor is a P-channel type transistor, and said second and third MIS transistors are N-channel type transistors connected in series between said output side of said first MIS transistor and said one of power supply lines having low potential level.
Claim 6
Dependent Claim
26 words
A transfer gate circuit according to claim 1, wherein said input signal of said inverter circuit is input from said input of said first MIS transistor.
Claim 7
Dependent Claim
26 words
A transfer gate circuit according to claim 1, wherein said input signal of said inverter circuit is input from said output of said first MIS transistor.
Claim 8
Dependent Claim
52 words
A transfer gate circuit according to claim 2, wherein said first MIS transistor is an N-channel type transistor, and said second and third MIS transistors are P-channel type transistors connected in series between said one of power supply lines having high potential level and said output side of said first MIS transistor.
Claim 9
Dependent Claim
52 words
A transfer gate circuit according to claim 2, wherein said first MIS transistor is a P-channel type transistor, and said second and third MIS transistors are N-channel type transistors connected in series between said output side of said first MIS transistor and said one of power supply lines having low potential level.
Claim 10
Dependent Claim
26 words
A transfer gate circuit according to claim 2, wherein said input signal of said inverter circuit is input from said input of said first MIS transistor.
Claim 11
Dependent Claim
26 words
A transfer gate circuit according to claim 2, wherein said input signal of said inverter circuit is input from said output of said first MIS transistor.
References Cited (Backward Citations)
US4563599A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-21 | 1992-08-22 | 1993-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-21 | 1996-08-22 | 1997-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-21 | 2000-08-22 | 2001-02-21 | $7700.00 | Window Closed / Lapsed |