Patent US5644247A successfully refreshed from Google Patents.
US5644247A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Test socket and method for producing known good dies using the test socket
Assignee: Samsung Electronics Co Ltd
•
Filing: 1996-05-09
•
Granted: 1997-07-01
•
Expires: 2016-05-09
Abstract
Abstract A test socket and a method for identifying a known good die using the test socket. The test socket includes a substrate having penetrating apertures, and land patterns formed around the penetrating apertures. The substrate has contact terminals at one side which are connected to the outside, and a protective casing is installed on the upper part of the substrate. After the semiconductor chips are mounted in the test socket by a piece of adhesive tape, to cover the penetrating apertures of the substrate, the bonding pads of the semiconductor chips and the land patterns of the substrate are connected to each other by wires. The test socket is then installed on a burn-in test board to carry out a burn-in test. The wires of the bare chips, which have been subjected to the burn-in test are cut by a cutting device, and a lower portion of each semiconductor chip corresponding to a known good die, is hit by an ejection pin through the penetrating apertures of the substrate to separate and obtain the known good dies. Accordingly, a plurality of known good dies may be obtained by carrying out one burn-in test.
Inventors
- 👤 In Ho Hyun
- 👤 Sang Hyeong Lee
- 👤 Il Ung Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:00
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2855; G01R31/286; G01R31/2863; G01R1/00; G01R1/02; G01R1/04; G01R1/0408; G01R1/0433; G01R1/0483; G01R1/0441; G01R1/0466; G01R31/2886; G01R31/316; G01R31/3161; H; H10; H10W; H10W72/00; H10W72/071; H10W72/073; H10W72/075; H10W72/50; H10W72/531; H10W72/536; H10W72/5363; H10W90/00; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
217 words
A test device for testing a plurality of unpackaged semiconductor chips, comprising: a substrate having a plurality of semiconductor chip-mounting locations thereon, said substrate including a plurality of openings extending through said substrate, each said opening positionally corresponding to a respective semiconductor chip mounting location; at least one piece of double-sided adhesive tape having one side adhered on said substrate at each said semiconductor chip-mounting location; said adhesive tape being configured to leave each of said openings effectively unobstructed thereby, and having another side disposed for removably adhesively mounting a respective unpackaged semiconductor chip to said substrate at a respective semiconductor chip-mounting location, while permitting demounting of the respective unpackaged semiconductor chip by effective engagement of the chip through the respective opening from an opposite side of the substrate from the respective semiconductor chip-mounting location using an effective pushing element; a plurality of conductive land patterns disposed about a periphery of each opening, wherein each said semiconductor chip mounting location does not overlap a corresponding said conductive land pattern; and a plurality of external contact sites formed along an edge of said substrate, said external contact sites being electrically connected to said plurality of conductive land patterns, said external contact sites being constructed and arranged to be connected with circuitry which is external to the test device.
Claim 2
Dependent Claim
217 words
A test device for testing a plurality of unpackaged semiconductor chips, comprising: a substrate having a plurality of semiconductor chip-mounting locations thereon, said substrate including a plurality of openings extending through said substrate, each said opening positionally corresponding to a respective semiconductor chip mounting location; at least one piece of double-sided adhesive tape having one side adhered on said substrate at each said semiconductor chip-mounting location; said adhesive tape being configured to leave each of said openings effectively unobstructed thereby, and having another side disposed for removably adhesively mounting a respective unpackaged semiconductor chip to said substrate at a respective semiconductor chip-mounting location, while permitting demounting of the respective unpackaged semiconductor chip by effective engagement of the chip through the respective opening from an opposite side of the substrate from the respective semiconductor chip-mounting location using an effective pushing element; a plurality of conductive land patterns disposed about a periphery of each opening, wherein each said semiconductor chip mounting location does not overlap a corresponding said conductive land pattern; and a plurality of external contact sites formed along an edge of said substrate, said external contact sites being electrically connected to said plurality of conductive land patterns, said external contact sites being constructed and arranged to be connected with circuitry which is external to the test device.
Claim 3
Dependent Claim
16 words
The test device as claimed in claim 1, wherein said substrate is formed from a ceramic.
Claim 4
Dependent Claim
50 words
The test device as claimed in claim 1, wherein said at least one piece of double-sided adhesive tape is constituted by a plurality of double-faced adhesive tape portions, each said tape portion having an opening formed therethrough which is aligned with a corresponding one of said openings of said substrate.
Claim 5
Dependent Claim
23 words
The test device as claimed in claim 3, wherein said tape portion can withstand a peak temperature associated with a chip burn-in test.
Claim 6
Dependent Claim
39 words
The test device as claimed in claim 1, further comprising a protective casing detachably engaged with said substrate, said casing protectively covering said plurality of openings and said plurality of land patterns while leaving said external contact sites exposed.
Claim 7
Dependent Claim
18 words
The test device as claimed in claim 5, wherein said casing is made from a static-electricity resistant material.
Claim 8
Dependent Claim
20 words
The test device as claimed in claim 5, wherein said protective casing is engaged with said substrate by a screw.
Claim 9
Dependent Claim
31 words
The test device as claimed in claim 1, wherein the external circuitry is a burn-in test circuit having a plurality of receiving portions for receiving a plurality of the test devices.
Claim 10
Dependent Claim
54 words
The test device as claimed in claim 8, wherein the receiving portions of the burn-in test circuit are a plurality of slot connectors, wherein said substrate includes an externally-protruding tab portion along which said external contact sites are provided, said tab portion being engageable in a respective slot connector of the burn-in test circuit.
Claim 11
Dependent Claim
16 words
The test device as claimed in claim 1, wherein said substrate is a printed circuit board.
Claim 12
Dependent Claim
211 words
A testing method for obtaining a plurality of known-good dies, comprising the steps of: mounting at least one semiconductor chip a plurality of unpackaged semiconductor chips on a test substrate having a plurality of semiconductor chip mounting locations provided thereon; the test substrate having a plurality of openings formed therethrough, each semiconductor chip being mounted on the test substrate so that it substantially covers a respective opening; said mounting including mounting each chip on the test substrate using double-faced adhesive tape which is sized, shaped and positioned so as to leave each said opening effectively unobstructed by said adhesive tape; electrically connecting each semiconductor chip to the test substrate; connecting the test substrate to a burn-in test board such that each semiconductor chip is electrically connected to the burn-in test board; performing a burn-in test on each semiconductor chip mounted on the test substrate; disconnecting the at least one semiconductor chip from electrical connection to the test substrate; and identifying and physically separating each semiconductor chip successfully passing the burn-in test from the substrate, including applying force through a respective opening in the test substrate against one side of each semiconductor chip, which has been identified as having passed the burn-in test and thereby demounting that chip from said adhesive tape.
Claim 13
Dependent Claim
211 words
A testing method for obtaining a plurality of known-good dies, comprising the steps of: mounting at least one semiconductor chip a plurality of unpackaged semiconductor chips on a test substrate having a plurality of semiconductor chip mounting locations provided thereon; the test substrate having a plurality of openings formed therethrough, each semiconductor chip being mounted on the test substrate so that it substantially covers a respective opening; said mounting including mounting each chip on the test substrate using double-faced adhesive tape which is sized, shaped and positioned so as to leave each said opening effectively unobstructed by said adhesive tape; electrically connecting each semiconductor chip to the test substrate; connecting the test substrate to a burn-in test board such that each semiconductor chip is electrically connected to the burn-in test board; performing a burn-in test on each semiconductor chip mounted on the test substrate; disconnecting the at least one semiconductor chip from electrical connection to the test substrate; and identifying and physically separating each semiconductor chip successfully passing the burn-in test from the substrate, including applying force through a respective opening in the test substrate against one side of each semiconductor chip, which has been identified as having passed the burn-in test and thereby demounting that chip from said adhesive tape.
Claim 14
Dependent Claim
39 words
The testing method as claimed in claim 11, wherein said step of electrically connecting each semiconductor chip to the test substrate comprises connecting each semiconductor chip to the test substrate using a respective wire bonded to each semiconductor chip.
Claim 15
Dependent Claim
27 words
The testing method as claimed in claim 12, wherein said disconnection step comprises a step of cutting the wire connecting each semiconductor chip and the test substrate.
Claim 16
Dependent Claim
27 words
The testing method as claimed in claim 13, wherein said cutting step is performed by one of a cutting blade, a cutting laser, and a chisel-headed cutter.
Claim 17
Dependent Claim
79 words
The testing method as claimed in claim 13, wherein said step of electrically connecting each semiconductor chip to the test substrate includes using a respective wire which is ball-bonded to the respective semiconductor chip so as to form a conductive ball portion on the respective semiconductor chip, and wherein said disconnection step comprises cutting each wire at the respective conductive ball portion so as to leave a portion of the respective conductive ball portion on the respective semiconductor chip.
Claim 18
Dependent Claim
42 words
The testing method as claimed in claim 13, wherein said disconnection step comprises cutting each wire so as to leave a portion of respective wire on the respective semiconductor chip, thereby forming a respective connection bump having a substantially flat cut surface.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-30 | 2000-12-30 | 2001-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-30 | 2004-12-30 | 2005-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-30 | 2008-12-30 | 2009-07-01 | $7700.00 | Window Closed / Lapsed |