US5378981A
Expired / Lapsed
US
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Method for testing a semiconductor device on a universal test circuit substrate
Assignee: NXP USA Inc
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Filing: 1993-02-02
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Granted: 1995-01-03
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Expires: 2013-02-02
Abstract
Abstract A low cost method is used to standardize testing of bare semiconductor devices. In one embodiment, a universal test circuit substrate (10) having an interleaving fan-out pattern of conductive traces (14) is provided. The radial array of conductive traces terminates in a plurality of test pads (16) placed in a standard pattern around a periphery of a central die accommodating region. A die cavity (36), slightly larger than the size of a semiconductor die (32) to be tested, is formed in the central die accommodating region. The semiconductor die is placed approximately centered in the die cavity and is wire bonded (40) to individual traces of the pattern of conductive traces. The die can be tested and burned-in on the universal test circuit substrate with a test probe making contact with the test pads. The universal test circuit substrate can accommodate a multiplicity of die sizes and pin-out requirements of semiconductor devices.
Inventors
- 👤 Leo M. Higgins, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:04
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/688; G; G01; G01R; G01R31/00; G01R31/28; G01R31/282; G01R31/2831; G01R31/2851; G01R31/2884; H10P; H10P72/00; H10P72/70; H10P72/74; H10W70/40; H10W70/453; H10W72/00; H10W72/071; H10W72/073; H10W72/07351; H10W72/07353; H10W72/075; H10W72/07531; H10W72/07532; H10W72/07533; H10W72/07551; H10W72/07554; H10W72/30; H10W72/331; H10W72/334; H10W72/50; H10W72/541; H10W72/5449; H10W72/547; H10W72/5473; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/851; H10W72/874; H10W72/884; H10W72/90; H10W72/931; H10W72/932; H10W90/00; H10W90/701; H10W90/731; H10W90/734; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
153 words
A method for testing a semiconductor device comprising the steps of: providing a universal test circuit substrate comprising: an insulating film of electrically nonconductive material having a surface; and first and second interleaving fan-out patterns of conductive traces extending radially outward on the surface of the insulating layer, wherein the first and second interleaving fan-out patterns of conductive traces initiate from different predetermined distances from a central die accommodating region and terminate in a plurality of test pads in an offset pattern around a distal periphery of the central die accommodating region, wherein said test pads are sufficiently large to enable electrical contact to test contactors; placing a semiconductor die in the central die accommodating region; wire bonding the semiconductor die to some the conductive traces to provide electrical connections; and testing the semiconductor die via the plurality of test pads prior to excising the semiconductor die from the universal test circuit substrate.
Claim 2
Independent Claim
153 words
A method for testing a semiconductor device comprising the steps of: providing a universal test circuit substrate comprising: an insulating film of electrically nonconductive material having a surface; and first and second interleaving fan-out patterns of conductive traces extending radially outward on the surface of the insulating layer, wherein the first and second interleaving fan-out patterns of conductive traces initiate from different predetermined distances from a central die accommodating region and terminate in a plurality of test pads in an offset pattern around a distal periphery of the central die accommodating region, wherein said test pads are sufficiently large to enable electrical contact to test contactors; placing a semiconductor die in the central die accommodating region; wire bonding the semiconductor die to some the conductive traces to provide electrical connections; and testing the semiconductor die via the plurality of test pads prior to excising the semiconductor die from the universal test circuit substrate.
Claim 3
Dependent Claim
35 words
The method of claim 1, wherein the step of placing the semiconductor die comprises mounting the semiconductor die on the central die accommodating region of the universal test circuit substrate using an electrically insulating adhesive.
Claim 4
Dependent Claim
44 words
The method of claim 1, further comprising the step of: forming a die cavity in the universal test circuit substrate in the central die accommodating region, the die cavity having a size substantially equal to a size of the semiconductor die plus a clearance.
Claim 5
Dependent Claim
29 words
The method of claim 1, wherein the step of wire bonding comprises a technique selected from a group of: thermosonic wire bonding, ultrasonic wire bonding, and thermocompression wire bonding.
Claim 6
Dependent Claim
20 words
The method of claim 1 further comprising the step of: burning-in the semiconductor die via the plurality of test pads.
Claim 7
Dependent Claim
70 words
The method of claim 1, wherein the step of providing a universal test circuit substrate comprises providing a material selected from a group consisting of: conductor patterned polymer film, aluminum on polyester film, copper on polyester film, aluminum on polyimide film, copper on polyimide film, conductor patterned reinforced polymer film, copper on epoxy-glass, aluminum on epoxy-glass, copper on phenolic-paper, aluminum on phenolic paper, copper on polyimide-glass, and aluminum on polyimide-glass.
Claim 8
Dependent Claim
28 words
The method of claim 1, wherein the step of providing a universal test circuit substrate comprise providing a universal test circuit substrate having a plurality of conductor planes.
Claim 9
Independent Claim
213 words
A method for testing a semiconductor device comprising the steps of: providing a universal test circuit substrate comprising: an insulating film of electrically nonconductive material having a surface; first and second interleaving fan-out patterns of conductive traces extending radially outward on the surface of the insulating layer, wherein the first and second interleaving fan-out patterns of conductive traces initiate from different predetermined distances from a central die accommodating region and terminate in a plurality of test pads in an offset pattern around a distal periphery of the central die accommodating region, wherein said test pads are sufficiently large to enable electrical contact to test contactors; and a plurality of excise regions in a central die accommodating region; providing a semiconductor die having a size; forming a die cavity in the universal test circuit substrate corresponding to one of the plurality of excise regions in the central die accommodating region, the die cavity being of a size substantially equal to the size of the semiconductor die plus a clearance; wire bonding the semiconductor die to a portion of the plurality of interleaving fan-out patterns of conductive traces to provide electrical connections; and testing the semiconductor die via the plurality of test pads prior to excising the semiconductor die from the universal test circuit substrate.
Claim 10
Independent Claim
213 words
A method for testing a semiconductor device comprising the steps of: providing a universal test circuit substrate comprising: an insulating film of electrically nonconductive material having a surface; first and second interleaving fan-out patterns of conductive traces extending radially outward on the surface of the insulating layer, wherein the first and second interleaving fan-out patterns of conductive traces initiate from different predetermined distances from a central die accommodating region and terminate in a plurality of test pads in an offset pattern around a distal periphery of the central die accommodating region, wherein said test pads are sufficiently large to enable electrical contact to test contactors; and a plurality of excise regions in a central die accommodating region; providing a semiconductor die having a size; forming a die cavity in the universal test circuit substrate corresponding to one of the plurality of excise regions in the central die accommodating region, the die cavity being of a size substantially equal to the size of the semiconductor die plus a clearance; wire bonding the semiconductor die to a portion of the plurality of interleaving fan-out patterns of conductive traces to provide electrical connections; and testing the semiconductor die via the plurality of test pads prior to excising the semiconductor die from the universal test circuit substrate.
Claim 11
Dependent Claim
70 words
The method of claim 8 wherein the step of providing a universal test circuit substrate comprises providing a material selected from a group consisting of: conductor patterned polymer film, aluminum on polyester film, copper on polyester film, aluminum on polyimide film, copper on polyimide film, conductor patterned reinforced polymer film, copper on epoxy-glass, aluminum on epoxy-glass, copper on phenolic-paper, aluminum on phenolic paper, copper on polyimide-glass, and aluminum on polyimide-glass.
Claim 12
Dependent Claim
30 words
The method of claim 8 wherein the step of forming a die cavity is performed by a using a method selected from a group consisting of: mechanical, laser, and etching.
Claim 13
Dependent Claim
28 words
The method of claim 8, wherein the step of providing a universal test circuit substrate comprise providing a universal test circuit substrate having a plurality of conductor planes.
Claim 14
Dependent Claim
29 words
The method of claim 8 wherein the step of wire bonding comprises a technique selected from a group of: thermosonic wire bonding, ultrasonic wire bonding, and thermocompression wire bonding.
Claim 15
Dependent Claim
20 words
The method of claim 8 further comprising the step of: burning-in the semiconductor die via the plurality of test pads.
Claim 16
Independent Claim
182 words
A method for testing a semiconductor device comprising the steps of: providing a universal test circuit substrate comprising: an insulating film for electrically nonconductive material having a surface; and first and second interleaving fan-out patterns of conductive traces extending radially outward on the surface of the insulating layer, wherein the first and second interleaving fan-out patterns of conductive traces initiate from different predetermined distances from a central die accommodating region and terminate in a plurality of test pads in an offset pattern around a distal periphery of the central die accommodating region, wherein said test pads are sufficiently large to enable electrical contact to test contactors; and attaching a semiconductor die on the universal test circuit substrate using an electrically insulating adhesive, wherein a portion of the semiconductor die overlies the first fan-out pattern of conductive traces; wire bonding the semiconductor die to a portion of the plurality of interleaving fan-out patterns of conductive traces to provide electrical connections; and testing the semiconductor die via the plurality of test pads prior to excising the semiconductor die from the universal test circuit substrate.
Claim 17
Independent Claim
182 words
A method for testing a semiconductor device comprising the steps of: providing a universal test circuit substrate comprising: an insulating film for electrically nonconductive material having a surface; and first and second interleaving fan-out patterns of conductive traces extending radially outward on the surface of the insulating layer, wherein the first and second interleaving fan-out patterns of conductive traces initiate from different predetermined distances from a central die accommodating region and terminate in a plurality of test pads in an offset pattern around a distal periphery of the central die accommodating region, wherein said test pads are sufficiently large to enable electrical contact to test contactors; and attaching a semiconductor die on the universal test circuit substrate using an electrically insulating adhesive, wherein a portion of the semiconductor die overlies the first fan-out pattern of conductive traces; wire bonding the semiconductor die to a portion of the plurality of interleaving fan-out patterns of conductive traces to provide electrical connections; and testing the semiconductor die via the plurality of test pads prior to excising the semiconductor die from the universal test circuit substrate.
Claim 18
Dependent Claim
70 words
The method of claim 14 wherein the step of providing a universal test circuit substrate comprises providing a material selected from a group consisting of: conductor patterned polymer film, aluminum on polyester film, copper on polyester film, aluminum on polyimide film, copper on polyimide film, conductor patterned reinforced polymer film, copper on epoxy-glass, aluminum on epoxy-glass, copper on phenolic-paper, aluminum on phenolic paper, copper on polyimide-glass, and aluminum on polyimide-glass.
Claim 19
Dependent Claim
28 words
The method of claim 14, wherein the step of providing a universal test circuit substrate comprise providing a universal test circuit substrate having a plurality of conductor planes.
Claim 20
Dependent Claim
29 words
The method of claim 14 wherein the step of wire bonding comprises a technique selected from a group of: thermosonic wire bonding, ultrasonic wire bonding, and thermocompression wire bonding.
Claim 21
Dependent Claim
20 words
The method of claim 14 further comprising the step of: burning-in the semiconductor die via the plurality of test pads.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-01-02 | 1998-07-04 | 1999-01-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-02 | 2002-07-04 | 2003-01-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-02 | 2006-07-04 | 2007-01-03 | $7700.00 | Window Closed / Lapsed |