US5247248A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Burn-in apparatus and method of use thereof
Assignee: Sharp Corp
•
Filing: 1992-02-07
•
Granted: 1993-09-21
•
Expires: 2012-02-07
Abstract
Abstract In order to improve the operability of a burn-in apparatus, to shorten the operating time, to reduce the number of the components, and to increase the package density of semiconductor integrated circuits to be accommodated within a burn-in apparatus, semiconductor integrated circuits with a lead frame are mounted on a first wiring board by means of fixing the pressuring member to the first wiring board with a magnetic force. Thereafter, the first wiring board is mounted to a second wiring board, and both are to be inserted into a burn-in apparatus.
Inventors
- 👤 Satoru Fukunaga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:43
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2855; G01R31/286; G01R31/2863; G01R31/2862; H; H05; H05K; H05K1/00; H05K1/02; H05K1/14; H05K3/00; H05K3/30; H05K3/32; H05K3/325
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
129 words
A burn-in apparatus comprising: a plurality of mounting members, each of said mounting members including, a first wiring board having a plurality of mounting locations for arranging and setting therein each of a plurality of semiconductor integrated circuit elements, and pressuring member which is attracted and fixed to the first wiring board by a magnetic force so as to fasten the semiconductor integrated circuit elements wherein at least either of the first wiring board or the pressuring member is selected according to the type of the semiconductor integrated circuit elements; a second wiring board on which said plurality of mounting members are mounted with one end thereof in an erect manner from the second wiring board; and a housing apparatus for burn-in testing which accommodates the second wiring board.
Claim 2
Dependent Claim
129 words
A burn-in apparatus comprising: a plurality of mounting members, each of said mounting members including, a first wiring board having a plurality of mounting locations for arranging and setting therein each of a plurality of semiconductor integrated circuit elements, and pressuring member which is attracted and fixed to the first wiring board by a magnetic force so as to fasten the semiconductor integrated circuit elements wherein at least either of the first wiring board or the pressuring member is selected according to the type of the semiconductor integrated circuit elements; a second wiring board on which said plurality of mounting members are mounted with one end thereof in an erect manner from the second wiring board; and a housing apparatus for burn-in testing which accommodates the second wiring board.
Claim 3
Dependent Claim
27 words
A burn-in apparatus according to claim 1 wherein said plurality of semiconductor integrated circuit elements, which include a lead frame, are disposed on the first wiring board.
Claim 4
Dependent Claim
45 words
A burn-in apparatus according to claim 2 wherein each of said mounting members further comprises a plurality of locating openings and locating pins provided on said first wiring board for positioning and aligning said lead frame and said pressuring member on said first wiring board.
Claim 5
Dependent Claim
39 words
A burn-in apparatus according to claim 1 wherein the mounting locations for disposing said plurality of integrated circuit elements on said first wiring board are made up of a pressure conductive rubber sheet disposed over the first wiring board.
Claim 6
Dependent Claim
25 words
A burn-in apparatus according to claim 1 wherein the semiconductor integrated circuit elements to undergo burn-in testing comprise flat package type semiconductor integrated circuit elements.
Claim 7
Dependent Claim
25 words
A burn-in apparatus according to claim 1 wherein the semiconductor integrated circuit elements to undergo burn-in testing comprise dual line type semiconductor integrated circuit elements.
Claim 8
Dependent Claim
151 words
A burn-in method comprising the steps of: (a) preparing a semiconductor integrated circuit member wherein a plurality of semiconductor integrated circuit elements are connected to a supporting member and lead terminals project from the semiconductor integrated circuit elements; (b) arranging the semiconductor integrated circuit member in such a way that each of the semiconductor integrated circuit elements is mounted in a respective mounting location set on the first wiring board; (c) fixing the semiconductor integrated circuit member onto the first wiring board by a pressuring member with a magnetic force; (d) mounting a plurality of mounting members, to which the semiconductor integrated circuit member is secured, to the second wiring board with one end of each of the mounting members in an erect manner; (e) placing the second wiring board with the mounting members in a burn-in apparatus housing; and (f) performing a burn-in testing on the semiconductor integrated circuit elements.
Claim 9
Dependent Claim
151 words
A burn-in method comprising the steps of: (a) preparing a semiconductor integrated circuit member wherein a plurality of semiconductor integrated circuit elements are connected to a supporting member and lead terminals project from the semiconductor integrated circuit elements; (b) arranging the semiconductor integrated circuit member in such a way that each of the semiconductor integrated circuit elements is mounted in a respective mounting location set on the first wiring board; (c) fixing the semiconductor integrated circuit member onto the first wiring board by a pressuring member with a magnetic force; (d) mounting a plurality of mounting members, to which the semiconductor integrated circuit member is secured, to the second wiring board with one end of each of the mounting members in an erect manner; (e) placing the second wiring board with the mounting members in a burn-in apparatus housing; and (f) performing a burn-in testing on the semiconductor integrated circuit elements.
References Cited (Backward Citations)
US4636726A
Cited
JPS5976456A
Cited
JPS611897A
Cited
US4871963A
Cited
US4926117A
Cited
US5008614A
Cited
US4985988A
Cited
US5086269A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-09-20 | 1997-03-22 | 1997-09-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-20 | 2001-03-22 | 2001-09-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-20 | 2005-03-22 | 2005-09-21 | $7700.00 | Window Closed / Lapsed |