Ball grid array package for a integrated circuit

Claim 2

A ball grid array ("BGA") package for an integrated circuit ("IC") having improved BGA package thermal and electrical characteristics, comprising: upper layer BGA package traces including a Vss trace, a Vdd trace, and a signal trace; lower layer BGA package traces at least a portion of which traces are in vertical alignment with a corresponding one of said upper layer BGA package traces; wherein regions of said lower layer BGA package traces are solderable to solder balls used to solder said BGA package to an underlying system printed circuit board; BGA core material disposed between said upper and lower layer BGA package traces; vias including a unitary-construction Vss via coupling said upper layer BGA Vss trace to a corresponding lower layer BGA Vss trace, a unitary-construction Vdd via coupling said upper layer BGA Vdd trace to a corresponding lower layer BGA Vdd trace, and a unitary-construction signal via coupling a said upper layer BGA signal trace to a corresponding lower layer BGA signal trace; and a BGA Vss plane, disposed intermediate said upper and lower layer BGA package traces and making electrical contact with said Vss via.

Claim 3

The package of claim 1, further including a BGA Vdd plane, disposed intermediate said BGA Vss plane and said lower layer BGA package traces and making electrical contact with said Vdd via.

Claim 4

The package of claim 1, wherein a chosen one of (a) said upper layer BGA package traces, a portion of said BGA core material and said BGA Vss plane, and (b) said BGA Vdd plane, a portion of said BGA core material, and said lower layer BGA package traces comprises doubled-sided printed circuit board material.

Claim 5

The package of claim 1, wherein said BGA core material includes a material selected from the group consisting of (a) FR4 epoxy glass, and (b) pre-preg.

Claim 6

The package of claim 1, wherein said BGA Vss plane is vertically spaced-apart from a substrate of said IC a distance less than about 0.03" (0.8 mm).

Claim 7

The package of claim 1, wherein said upper layer BGA package Vss trace includes a BGA package IC die plane that is soldered to a substrate of said IC.

Claim 8

The package of claim 1, wherein said package results in an output impedance between a signal output pad on said IC and said Vss plane of about 50 Ω.

Claim 9

A three-layer ball grid array ("BGA") package for an integrated circuit ("IC") having improved BGA package thermal and electrical characteristics, comprising: a first BGA core sandwiched between first and second surfaces clad with conductive material; said conductive material on said first surface defining at least a first BGA package surface Vdd plane, a first BGA package surface signal trace, and a first BGA package surface Vss plane said conductive material on said second surface forming a BGA Vss plane having at least three via openings defined therethrough; a second BGA core whose first surface contacts said BGA Vss plane, and whose second surface defines at least a second BGA package surface Vdd plane a portion of which is in vertical registration with said first BGA package surface Vdd plane, a second BGA package surface signal trace a portion of which is in vertical registration with said first BGA package surface signal trace, and a second BGA package surface Vss plane a portion of which is in vertical registration with said first BGA package surface Vss plane; a unitary-construction Vdd via coupling said first BGA package surface Vdd plane and said second BGA package surface Vdd plane and passing through a via opening in said BGA Vss plane without contacting said BGA Vss plane; a unitary-construction signal via coupling said first BGA package surface signal trace and said second BGA package surface signal trace and passing through an opening in said BGA Vss plane without contacting said BGA Vss plane; and a unitary-construction Vss via coupling said first BGA package surface Vss plane and said second BGA package surface Vss plane and passing through an opening in said BGA Vss plane while contacting said BGA Vss plane; wherein said IC includes a substrate coupled to a chosen one of said first BGA package surface Vss plane and said second BGA package surface Vss plane, and wherein said IC further includes a signal pad coupled by a bond wire to a signal trace on the chosen first or second BGA package surface to which said substrate is coupled, and wherein said IC further includes a Vdd pad coupled by a bond wire to a Vdd plane on the chosen first or second BGA package surface to which said substrate is coupled; wherein solder balls contact traces and planes on the unchosen of said first or second BGA package surface.

Claim 10

A three-layer ball grid array ("BGA") package for an integrated circuit ("IC") having improved BGA package thermal and electrical characteristics, comprising: a first BGA core sandwiched between first and second surfaces clad with conductive material; said conductive material on said first surface defining at least a first BGA package surface Vdd plane, a first BGA package surface signal trace, and a first BGA package surface Vss plane said conductive material on said second surface forming a BGA Vss plane having at least three via openings defined therethrough; a second BGA core whose first surface contacts said BGA Vss plane, and whose second surface defines at least a second BGA package surface Vdd plane a portion of which is in vertical registration with said first BGA package surface Vdd plane, a second BGA package surface signal trace a portion of which is in vertical registration with said first BGA package surface signal trace, and a second BGA package surface Vss plane a portion of which is in vertical registration with said first BGA package surface Vss plane; a unitary-construction Vdd via coupling said first BGA package surface Vdd plane and said second BGA package surface Vdd plane and passing through a via opening in said BGA Vss plane without contacting said BGA Vss plane; a unitary-construction signal via coupling said first BGA package surface signal trace and said second BGA package surface signal trace and passing through an opening in said BGA Vss plane without contacting said BGA Vss plane; and a unitary-construction Vss via coupling said first BGA package surface Vss plane and said second BGA package surface Vss plane and passing through an opening in said BGA Vss plane while contacting said BGA Vss plane; wherein said IC includes a substrate coupled to a chosen one of said first BGA package surface Vss plane and said second BGA package surface Vss plane, and wherein said IC further includes a signal pad coupled by a bond wire to a signal trace on the chosen first or second BGA package surface to which said substrate is coupled, and wherein said IC further includes a Vdd pad coupled by a bond wire to a Vdd plane on the chosen first or second BGA package surface to which said substrate is coupled; wherein solder balls contact traces and planes on the unchosen of said first or second BGA package surface.

Claim 11

The package of claim 8, wherein said first BGA core sandwiched between first and second surfaces clad with conductive material comprises a double-sided printed circuit board.

Claim 12

The package of claim 8, wherein said BGA Vss plane is vertically spaced-apart from said substrate of said IC a distance less than about 0.03" (0.8 mm).

Claim 13

The package of claim 8, wherein at least one of said first and second BGA core includes a material selected from the group consisting of (a) FR4 epoxy glass, and (b) pre-preg.

Claim 14

The package of claim 1, wherein said IC includes a digital circuit operating at a frequency of at least 30 MHz.

Claim 15

A four-layer ball grid array ("BGA") package for an integrated circuit ("IC") having improved BGA package thermal and electrical characteristics, comprising: a first BGA core sandwiched between first and second surfaces clad with conductive material; said conductive material on said first surface defining at least a first BGA package surface Vdd plane, a first BGA package surface signal trace, and a first BGA package surface Vss plane said conductive material on said second surface forming a BGA Vss plane having at least three via openings defined therethrough; a second BGA core sandwiched between first and second surfaces clad with conductive material; said conductive material on said first surface defining a BGA Vdd plane and having at least three via openings defined therethrough; said conductive material on said second surface defining at least a second BGA package surface Vdd plane a portion of which is in vertical alignment with said first BGA package surface Vdd plane, a second BGA package surface signal trace a portion of which is in vertical alignment with said first BGA package surface signal trace, and a second BGA package surface Vss plane a portion of which is in vertical registration with said first BGA package surface Vss plane; a unitary-construction Vdd via coupling said first BGA package surface Vdd plane, said second BGA package surface Vdd plane, and said BGA Vdd plane by passing through a via opening therein while contacting said BGA Vdd plane, said unitary-construction Vdd via passing through a via opening in said BGA Vss plane without contacting said BGA Vss plane; a unitary-construction signal via coupling said first BGA package surface signal trace and said second BGA package surface signal trace and passing through vertically aligned via openings in said BGA Vss plane and in said BGA Vdd plane without contacting either said BGA Vss plane and BGA Vdd plane; a unitary-construction Vss via coupling said first BGA package surface Vss plane, said second BGA package surface Vss plane, and said BGA Vss plane by passing through a via opening therein while contacting said BGA Vss plane, said unitary-construction Vss via passing through a via opening in said BGA Vdd plane without contacting said BGA Vdd plane; and a third BGA core, disposed intermediate said BGA Vss plane and said BGA Vdd plane; wherein said IC includes a substrate coupled to said first BGA package surface Vss plane, and further includes a signal pad coupled to a bond wire coupled to said first BGA package signal trace, and further includes a Vdd pad coupled to a bond wire coupled to said first BGA package Vdd plane; wherein solder balls contact traces and planes on said second surface of said second BGA core.

Claim 16

A four-layer ball grid array ("BGA") package for an integrated circuit ("IC") having improved BGA package thermal and electrical characteristics, comprising: a first BGA core sandwiched between first and second surfaces clad with conductive material; said conductive material on said first surface defining at least a first BGA package surface Vdd plane, a first BGA package surface signal trace, and a first BGA package surface Vss plane said conductive material on said second surface forming a BGA Vss plane having at least three via openings defined therethrough; a second BGA core sandwiched between first and second surfaces clad with conductive material; said conductive material on said first surface defining a BGA Vdd plane and having at least three via openings defined therethrough; said conductive material on said second surface defining at least a second BGA package surface Vdd plane a portion of which is in vertical alignment with said first BGA package surface Vdd plane, a second BGA package surface signal trace a portion of which is in vertical alignment with said first BGA package surface signal trace, and a second BGA package surface Vss plane a portion of which is in vertical registration with said first BGA package surface Vss plane; a unitary-construction Vdd via coupling said first BGA package surface Vdd plane, said second BGA package surface Vdd plane, and said BGA Vdd plane by passing through a via opening therein while contacting said BGA Vdd plane, said unitary-construction Vdd via passing through a via opening in said BGA Vss plane without contacting said BGA Vss plane; a unitary-construction signal via coupling said first BGA package surface signal trace and said second BGA package surface signal trace and passing through vertically aligned via openings in said BGA Vss plane and in said BGA Vdd plane without contacting either said BGA Vss plane and BGA Vdd plane; a unitary-construction Vss via coupling said first BGA package surface Vss plane, said second BGA package surface Vss plane, and said BGA Vss plane by passing through a via opening therein while contacting said BGA Vss plane, said unitary-construction Vss via passing through a via opening in said BGA Vdd plane without contacting said BGA Vdd plane; and a third BGA core, disposed intermediate said BGA Vss plane and said BGA Vdd plane; wherein said IC includes a substrate coupled to said first BGA package surface Vss plane, and further includes a signal pad coupled to a bond wire coupled to said first BGA package signal trace, and further includes a Vdd pad coupled to a bond wire coupled to said first BGA package Vdd plane; wherein solder balls contact traces and planes on said second surface of said second BGA core.

Claim 17

The package of claim 13, wherein at least one of said first BGA core sandwiched between first and second surfaces clad with conductive material, and said second BGA core sandwiched between first and second surfaces clad with conductive material comprise a double-sided printed circuit board.

Claim 18

The package of claim 13, wherein said BGA Vss plane is disposed closer to said IC than is said BGA Vdd plane.

Claim 19

The package of claim 13, wherein said BGA Vss plane is vertically spaced-apart from said substrate of said IC a distance less than about 0.03" (0.8 mm).

Claim 20

The package of claim 13, wherein at least one of said first BGA core, said second BGA core, and said third BGA core includes a material selected from the group consisting of (a) FR4 epoxy glass, and (b) pre-preg.

Claim 21

The package of claim 13, further including an overmold encapsulating said IC.

Claim 22

The package of claim 13, wherein said IC includes a digital circuit operating at a frequency of at least 30 MHz.

Claim 23

The package of 13, wherein said package results in an output impedance between a signal output pad on said IC and one of said first BGA package surface Vss plane and said second BGA package surface Vss plane of about 50 Ω.

Claim 24

The package of 13, wherein said package results in an output impedance between a signal output pad on said IC and one of said first BGA package surface Vss plane and said second BGA package surface Vss plane of about 50 Ω.

Claim 25

The package of claim 13, wherein said IC includes a digital circuit operating at a frequency of at least 30 MHz.

Claim 26

The package of 8, wherein said package results in an output impedance between a signal output pad on said IC and said first BGA package surface Vss plane of about 50 Ω.

Claim 27

The package of 8, wherein said package results in an output impedance between a signal output pad on said IC and said first BGA package surface Vss plane of about 50 Ω.

Claim 28

The package of claim 1, wherein: said upper layer BGA package traces include a first Vss trace disposed over a center region of said package, and a second Vss trace disposed over a peripheral region of said package; and further including a first unitary-construction Vss via coupling said first Vss trace to a corresponding lower layer BGA first Vss trace, and a second unitary-construction Vss via coupling said second Vss trace to a corresponding lower layer BGA second Vss trace.

Claim 29

The package of claim 8, wherein: said first BGA package surface Vss plane includes a first Vss trace disposed over a center region of said package, and a second Vss trace disposed over a peripheral region of said package; said second BGA package surface Vss plane includes a first Vss trace disposed under a center region of said package, and a second Vss trace disposed under a peripheral region of said package; and further including: a first unitary-construction Vss via coupling said first Vss trace on said first BGA package surface Vss plane to said first Vss trace on said second BGA package surface Vss plane; and a second unitary-construction Vss via coupling said second Vss trace on said first BGA package surface Vss plane to said second Vss trace on said second BGA package surface Vss plane.

Claim 30

The package of claim 13, wherein: with respect to said first BGA core, said first BGA package surface Vss plane includes a first Vss trace disposed over a center region of said package, and a second Vss trace disposed over a peripheral region of said package; with respect to said second BGA core, said second BGA package surface Vss plane includes a first Vss trace disposed under a center region of said package, and a second Vss trace disposed under a peripheral region of said package; and further including: a first unitary-construction Vss via coupling said first Vss trace on said first BGA package surface Vss plane of said first BGA core to said first Vss trace on said second BGA package surface Vss plane of said second BGA core; and a second unitary-construction Vss via coupling said second Vss trace on said first BGA package surface Vss plane of said first BGA core to said second Vss trace on said second BGA package surface Vss plane of said second BGA core.