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Patent US5637525A successfully refreshed from Google Patents.
US5637525A
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Method of forming a CMOS circuitry
Assignee: Micron Technology Inc
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Filing: 1995-10-20
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Granted: 1997-06-10
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Expires: 2015-10-20
Abstract
Abstract A method of forming a field effect transistor includes, a) providing a gate over a semiconductor substrate, the gate having a thickness; b) providing an insulating dielectric layer over the gate, the insulating dielectric layer being provided to a thickness which is greater than the gate thickness to provide an outer dielectric layer surface which is above the gate; c) patterning and etching the insulating dielectric layer to provide openings therethrough to the substrate to define and expose active area adjacent the gate for formation of one of PMOS type or NMOS type diffusion regions; d) providing a layer of conductive material over the insulating dielectric layer and within the openings; e) providing the one of PMOS or NMOS type diffusion regions within the substrate relative to the first openings; and f) etching back the conductive layer to define electrically conductive projections which are isolated from one another within the openings. The method has specific applicability to CMOS fabrication, and provision of overlying and differently conductively doped polysilicon layers which are chemical-mechanical polished in a common step.
Inventors
- 👤 Charles H. Dennison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 13:56
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/02; H10D84/03; H10D84/038; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
308 words
A method of forming CMOS integrated circuitry comprising the following steps: providing a series of field oxide regions and a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to the substrate for formation of an NMOS transistor, a second gate line being positioned relative to the substrate for formation of a PMOS transistor; providing an insulating dielectric layer over the field oxide regions and the gate lines, the insulating dielectric layer being provided to a thickness effective to provide an outer dielectric layer surface which is above the first and second gate lines; patterning and etching the insulating dielectric layer to provide first openings therethrough to the substrate to define and expose active area adjacent one of the first or second gate lines for formation of one of PMOS type or NMOS type diffusion regions; providing a first layer of conductive material over the insulating dielectric layer and within the first openings; providing the one of PMOS or NMOS type diffusion regions within the substrate relative to the first openings; patterning and etching the first layer of conductive material and the underlying insulating dielectric layer to provide second openings through both of the first layer of conductive material and the underlying insulating dielectric layer and to expose active area adjacent the other of the first or second gate lines for formation of the other of PMOS type or NMOS type diffusion regions; providing a second layer of conductive material over the first layer of conductive material and within the second openings; providing the other of PMOS or NMOS type diffusion regions within the substrate relative to the second openings; and in a common step, etching back the first and the second conductive layers to define electrically conductive projections which are isolated from one another within the first and the second openings.
Claim 2
Independent Claim
308 words
A method of forming CMOS integrated circuitry comprising the following steps: providing a series of field oxide regions and a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to the substrate for formation of an NMOS transistor, a second gate line being positioned relative to the substrate for formation of a PMOS transistor; providing an insulating dielectric layer over the field oxide regions and the gate lines, the insulating dielectric layer being provided to a thickness effective to provide an outer dielectric layer surface which is above the first and second gate lines; patterning and etching the insulating dielectric layer to provide first openings therethrough to the substrate to define and expose active area adjacent one of the first or second gate lines for formation of one of PMOS type or NMOS type diffusion regions; providing a first layer of conductive material over the insulating dielectric layer and within the first openings; providing the one of PMOS or NMOS type diffusion regions within the substrate relative to the first openings; patterning and etching the first layer of conductive material and the underlying insulating dielectric layer to provide second openings through both of the first layer of conductive material and the underlying insulating dielectric layer and to expose active area adjacent the other of the first or second gate lines for formation of the other of PMOS type or NMOS type diffusion regions; providing a second layer of conductive material over the first layer of conductive material and within the second openings; providing the other of PMOS or NMOS type diffusion regions within the substrate relative to the second openings; and in a common step, etching back the first and the second conductive layers to define electrically conductive projections which are isolated from one another within the first and the second openings.
Claim 3
Dependent Claim
64 words
The method of forming CMOS integrated circuitry of claim 1 wherein the first layer of conductive material comprises conductively doped polysilicon having a conductivity enhancing dopant concentration of at least 1×10 20 ions/cm 3 , and wherein the step of providing the one type diffusion regions comprises out-diffusing the conductivity enhancing dopant into the substrate from the conductively doped polysilicon of the first layer.
Claim 4
Dependent Claim
64 words
The method of forming CMOS integrated circuitry of claim 1 wherein the second layer of conductive material comprises conductively doped polysilicon having a conductivity enhancing dopant concentration of at least 1×10 20 ions/cm 3 , and wherein the step of providing the other type diffusion regions comprises out-diffusing the conductivity enhancing dopant into the substrate from the conductively doped polysilicon of the second layer.
Claim 5
Dependent Claim
118 words
The method of forming CMOS integrated circuitry of claim 1 wherein, the first layer of conductive material comprises conductively doped polysilicon having a conductivity enhancing dopant concentration of at least 1×10 20 ions/cm 3 , and wherein the step of providing the one type diffusion regions comprises out-diffusing the conductivity enhancing dopant into the substrate from the conductively doped polysilicon of the first layer; and the second layer of conductive material comprises conductively doped polysilicon having a conductivity enhancing dopant concentration of at least 1×10 20 ions/cm 3 , and wherein the step of providing the other type diffusion regions comprises out-diffusing the conductivity enhancing dopant into the substrate from the conductively doped polysilicon of the second layer.
Claim 6
Dependent Claim
132 words
The method of forming CMOS integrated circuitry of claim 1 wherein, the first layer of conductive material comprises conductively doped polysilicon having a conductivity enhancing dopant concentration of at least 1×10 20 ions/cm 3 , and wherein the step of providing the one type diffusion regions comprises out-diffusing the conductivity enhancing dopant into the substrate from the conductively doped polysilicon of the first layer; the second layer of conductive material comprises conductively doped polysilicon having a conductivity enhancing dopant concentration of at least 1×10 20 ions/cm 3 , and wherein the step of providing the other type diffusion regions comprises out-diffusing the conductivity enhancing dopant into the substrate from the conductively doped polysilicon of the second layer; and the out-diffusing to form the PMOS and the NMOS type diffusion regions occurs simultaneously.
Claim 7
Dependent Claim
19 words
The method of forming CMOS integrated circuitry of claim 1 wherein the etching back is conducted by chemical-mechanical polishing.
Claim 8
Dependent Claim
39 words
The method of forming CMOS integrated circuitry of claim 1 wherein the insulating dielectric layer is unplanarized prior to the common step, the common step also including etching of the insulating dielectric layer to provide an outer planarized surface.
Claim 9
Dependent Claim
45 words
The method of forming CMOS integrated circuitry of claim 1 wherein the insulating dielectric layer is unplanarized prior to the common step, the common step also including etching of the insulating dielectric layer to provide an outer planarized surface, the common step comprising chemical-mechanical polishing.
Claim 10
Dependent Claim
56 words
The method of forming CMOS integrated circuitry of claim 1 wherein the common step also includes etching of the insulating dielectric layer, the first gate line and the second gate line being covered with nitride caps, the common step comprising chemical-mechanical polishing of the insulating dielectric layer and using the nitride caps as an etch stop.
Claim 11
Dependent Claim
36 words
The method of forming CMOS integrated circuitry of claim 1 wherein the first and second openings are patterned to outwardly expose the essential entirety of the respective transistor active area not covered by the gate lines.
Claim 12
Dependent Claim
143 words
The method of forming CMOS integrated circuitry of claim 1 wherein, the first and second openings are patterned to outwardly expose the essential entirety of the respective transistor active area not covered by the gate lines; the first layer of conductive material comprises conductively doped polysilicon having a conductivity enhancing dopant concentration of at least 1×10 20 ions/cm 3 , and wherein the step of providing the one type diffusion regions comprises out-diffusing the conductivity enhancing dopant into the substrate from the conductively doped polysilicon of the first layer; and the second layer of conductive material comprises conductively doped polysilicon having a conductivity enhancing dopant concentration of at least 1×10 20 ions/cm 3 , and wherein the step of providing the other type diffusion regions comprises out-diffusing the conductivity enhancing dopant into the substrate from the conductively doped polysilicon of the second layer.
Claim 13
Dependent Claim
157 words
The method of forming CMOS integrated circuitry of claim 1 wherein, the first and second openings are patterned to outwardly expose the essential entirety of the respective transistor active area not covered by the gate lines; the first layer of conductive material comprises conductively doped polysilicon having a conductivity enhancing dopant concentration of at least 1×10 20 ions/cm 3 , and wherein the step of providing the one type diffusion regions comprises out-diffusing the conductivity enhancing dopant into the substrate from the conductively doped polysilicon of the first layer; the second layer of conductive material comprises conductively doped polysilicon having a conductivity enhancing dopant concentration of at least 1×10 20 ions/cm 3 , and wherein the step of providing the other type diffusion regions comprises out-diffusing the conductivity enhancing dopant into the substrate from the conductively doped polysilicon of the second layer; and the out-diffusing to form the PMOS and the NMOS type diffusion regions occurs simultaneously.
Claim 14
Dependent Claim
65 words
The method of forming CMOS integrated circuitry of claim 1 wherein, the first and second openings are patterned to outwardly expose the essential entirety of the respective transistor active area not covered by the gate lines; and the insulating dielectric layer is unplanarized prior to the common step, the common step also including etching of the insulating dielectric layer to provide an outer planarized surface.
Claim 15
Dependent Claim
71 words
The method of forming CMOS integrated circuitry of claim 1 wherein, the first and second openings are patterned to outwardly expose the essential entirety of the respective transistor active area not covered by the gate lines; and the insulating dielectric layer is unplanarized prior to the common step, the common step also including etching of the insulating dielectric layer to provide an outer planarized surface, the common step comprising chemical-mechanical polishing.
Claim 16
Dependent Claim
82 words
The method of forming CMOS integrated circuitry of claim 1 wherein, the first and second openings are patterned to outwardly expose the essential entirety of the respective transistor active area not covered by the gate lines; and the common step also includes etching of the insulating dielectric layer, the first gate line and the second gate line being covered with nitride caps, the common step comprising chemical-mechanical polishing of the insulating dielectric layer and using the nitride caps as an etch stop.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2000-06-09 | 2000-12-09 | 2001-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-09 | 2004-12-09 | 2005-06-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-09 | 2008-12-09 | 2009-06-10 | $7700.00 | Window Closed / Lapsed |