US5637519A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating a lightly doped drain thin-film transistor
Assignee: Industrial Technology Research Institute
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Filing: 1996-03-21
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Granted: 1997-06-10
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Expires: 2016-03-21
Abstract
Abstract A method of fabricating a lightly doped drain thin-film transistor having an inverted staggered structure is disclosed. The transistor has a glass substrate and a gate formed by a Cr layer on the substrate. An insulating layer and a semiconductor layer are deposited on the substrate and the gate. A first photo-resist layer is coated on top of the semiconductor layer. Back-side exposure and self-aligned technique are used to form an unexposed area slightly smaller than the gate area with high energy light. Low energy ion implantation is then performed on the exposed semiconductor layer to produce the lightly doped region. After removing the first photo-resist layer, another photo-resist process including a second photo-resist coating, back-side exposure and self-aligned technique is performed to form an unexposed area slightly larger than the gate area with low energy light. High energy ion implantation is then performed on the exposed semiconductor layer. The twice photo-resist processes and ion implantation processes result in a lightly doped drain.
Inventors
- 👤 Hsiung-Kuang Tsai
- 👤 Sheng-Kai Hwang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 19:50
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0316; H10D30/0321; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; Y; Y10; Y10S; Y10S430/00; Y10S430/1053; Y10S430/1055; Y10S430/114; Y10S430/12
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
307 words
A method of fabricating a lightly-doped drain thin-film transistor comprising the steps of: preparing a glass substrate; forming a gate area on a portion of said glass substrate; depositing an insulating layer above said gate area and said glass substrate; depositing a semiconductor layer over said insulating layer; forming a first photo-resist layer on said semiconductor layer; exposing said first photo-resist layer using said gate area as a self-aligned mask with a back-side exposure technique to slightly over expose said first photo-resist layer; developing said first photo-resist layer to form a first unexposed area slightly smaller than said gate area; establishing a lightly doped region in said semiconductor layer outside said first unexposed area on each side of said gate area; removing said first photo-resist layer from said first unexposed area; forming a second photo-resist layer on said semiconductor layer and the insulating layer; exposing said second photo-resist layer using said gate area as a self-aligned mask with a back-side exposure technique to slightly under expose said second photoresist layer; developing said second photo-resist layer to form a second unexposed area slightly larger than said gate area; establishing a heavily doped region in said semiconductor layer outside said second unexposed area on each side of said gate area; removing said second photo-resist layer from said second unexposed area; forming an island area by removing the outer portion of said semiconductor layer using a conventional photo-lithographic method, said island area comprising the first unexposed area, the lightly doped area, and the heavily doped area; establishing a drain above one end of said island area, said drain covering a portion of said heavily doped area and extending above said insulating layer; and forming a source above an opposite end of said island area, said source covering a portion of said heavily doped area and extending above said insulating layer.
Claim 2
Independent Claim
307 words
A method of fabricating a lightly-doped drain thin-film transistor comprising the steps of: preparing a glass substrate; forming a gate area on a portion of said glass substrate; depositing an insulating layer above said gate area and said glass substrate; depositing a semiconductor layer over said insulating layer; forming a first photo-resist layer on said semiconductor layer; exposing said first photo-resist layer using said gate area as a self-aligned mask with a back-side exposure technique to slightly over expose said first photo-resist layer; developing said first photo-resist layer to form a first unexposed area slightly smaller than said gate area; establishing a lightly doped region in said semiconductor layer outside said first unexposed area on each side of said gate area; removing said first photo-resist layer from said first unexposed area; forming a second photo-resist layer on said semiconductor layer and the insulating layer; exposing said second photo-resist layer using said gate area as a self-aligned mask with a back-side exposure technique to slightly under expose said second photoresist layer; developing said second photo-resist layer to form a second unexposed area slightly larger than said gate area; establishing a heavily doped region in said semiconductor layer outside said second unexposed area on each side of said gate area; removing said second photo-resist layer from said second unexposed area; forming an island area by removing the outer portion of said semiconductor layer using a conventional photo-lithographic method, said island area comprising the first unexposed area, the lightly doped area, and the heavily doped area; establishing a drain above one end of said island area, said drain covering a portion of said heavily doped area and extending above said insulating layer; and forming a source above an opposite end of said island area, said source covering a portion of said heavily doped area and extending above said insulating layer.
Claim 3
Dependent Claim
51 words
The method of fabricating a lightly-doped drain thin-film transistor according to claim 1, wherein an ion implantation process having sufficient energy for lightly doping said semiconductor layer is used for establishing said lightly doped region in said semiconductor layer outside said first unexposed area on each side of said gate area.
Claim 4
Dependent Claim
51 words
The method of fabricating a lightly-doped drain thin-film transistor according to claim 1, wherein an ion implantation process having substantial energy, for heavily doping said semiconductor layer is used for establishing said heavily doped region in said semiconductor layer outside said second unexposed area on each side of said gate area.
Claim 5
Dependent Claim
28 words
The method of fabricating a lightly-doped drain thin-film transistor according to claim 1, comprising the step of depositing an un-doped polysilicon layer to form as the semiconductor layer.
Claim 6
Dependent Claim
38 words
The method of fabricating a lightly-doped drain thin-film transistor according to claim 1, comprising the step of re-crystallizing an amorphous silicon into polysilicon by means of an anneal process or thermal treatment to form as the semiconductor layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-09 | 2000-12-09 | 2001-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-09 | 2004-12-09 | 2005-06-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-09 | 2008-12-09 | 2009-06-10 | $7700.00 | Window Closed / Lapsed |