Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
185 words
A method of fabrication a Thin Film Transistor comprising the steps of: forming a gate electrode around a central portion of a substrate; forming a gate insulating layer over the substrate so that the gate insulating layer can cover the gate electrode; forming a first semiconductor layer on the gate insulating layer; forming a sidewall spacer on both side surfaces of the first semiconductor layer in the vicinity of one and other sides of the gate electrode; forming a second semiconductor layer over the whole surface of the substrate; patterning the second semiconductor layer to form one of the patterned second semiconductor layers which is formed over the first semiconductor layer and apart from the one sidewall spacer by a constant distance in the vicinity of one side of the gate electrode, and simultaneously the other which is formed over the first semiconductor layer and the other sidewall spacer in the vicinity of the other side of the gate electrode; and diffusing an impurity in the second semiconductor layer through an anneal process to form highly doped impurity regions in the underlying first semiconductor layer.
Claim 2
Independent Claim
185 words
A method of fabrication a Thin Film Transistor comprising the steps of: forming a gate electrode around a central portion of a substrate; forming a gate insulating layer over the substrate so that the gate insulating layer can cover the gate electrode; forming a first semiconductor layer on the gate insulating layer; forming a sidewall spacer on both side surfaces of the first semiconductor layer in the vicinity of one and other sides of the gate electrode; forming a second semiconductor layer over the whole surface of the substrate; patterning the second semiconductor layer to form one of the patterned second semiconductor layers which is formed over the first semiconductor layer and apart from the one sidewall spacer by a constant distance in the vicinity of one side of the gate electrode, and simultaneously the other which is formed over the first semiconductor layer and the other sidewall spacer in the vicinity of the other side of the gate electrode; and diffusing an impurity in the second semiconductor layer through an anneal process to form highly doped impurity regions in the underlying first semiconductor layer.
Claim 3
Dependent Claim
15 words
A method of claim 1, wherein the first semiconductor layer comprises an undoped polysilicon layer.
Claim 4
Dependent Claim
16 words
A method of claim 1, wherein the first semiconductor layer comprises an undoped amorphous silicon layer.
Claim 5
Dependent Claim
22 words
A method of claim 1, further comprising the step of, after the step of forming the first semiconductor layer, implanting Si ion,
Claim 6
Dependent Claim
28 words
A method of claim 1, further comprising the step of, after the step of forming the first semiconductor layer, implanting an impurity ion for adjusting the threshold voltage.
Claim 7
Dependent Claim
21 words
A method of claim 1, wherein the second semiconductor layer is formed through depositing of an in situ doped semiconductor layer.
Claim 8
Dependent Claim
23 words
A method of claim 1, wherein the second semiconductor layer is formed by implanting impurity ions after deposition of an undoped semiconductor layer.
Claim 9
Dependent Claim
15 words
A method of claim 1, wherein the second semiconductor layer comprises a doped polysilicon layer.
Claim 10
Dependent Claim
16 words
A method of claim 1, wherein the second semiconductor layer comprises a doped amorphous silicon layer.