PLL circuit with improved stability

Claim 2

A PLL circuit comprising: phase comparing means for detecting a phase difference between a signal relating to an output of a voltage control oscillator and a reference signal, and discriminating between a phase lead and a phase lag; pulse generating means for generating a pulse signal having pulses a number of which corresponds to the phase difference detected by said phase comparing means; counting means for incrementing or decrementing a value which is previously set, by said number of pulses in accordance with the discrimination between the phase lead and the phase lag which is detected by said phase comparing means; converting means for converting a count value of said counting means into a voltage corresponding to the count value, and feeding the voltage back to said voltage control oscillator; and storage means for previously storing an initial value and setting the initial value to said counting means in response to a reset signal.

Claim 3

A PLL circuit comprising: voltage control oscillating means for oscillating at a frequency corresponding to an input voltage; first frequency dividing means for dividing the oscillation frequency of said voltage control oscillating means; reference signal generating means for outputting a reference signal; second frequency dividing means for dividing an output frequency of said reference signal generating means; phase comparing means for detecting a phase difference between an output signal of said first frequency dividing means and an output signal of said frequency dividing means, and discriminating between a phase lead and a phase lag; pulse generating means for generating a pulse signal having pulses a number of which corresponds to the phase difference detected by said phase comparing means; counting means for incrementing or decrementing a value which is previously set, by said number of pulses in accordance with the discrimination between the phase lead and the phase lag which is detected by said phase comparing means; converting means for converting a count value of said counting means into a voltage corresponding to the count value, and feeding the voltage back to said voltage control oscillating means; and storage means for previously storing an initial value and setting the initial value to said counting means in response to a reset signal.

Claim 4

A PLL circuit comprising: voltage control oscillating means for oscillating at a frequency corresponding to an input voltage; first frequency dividing means for dividing the oscillation frequency of said voltage control oscillating means; reference signal generating means for outputting a reference signal; second frequency dividing means for dividing an output frequency of said reference signal generating means; phase comparing means for detecting a phase difference between an output signal of said first frequency dividing means and an output signal of said frequency dividing means, and discriminating between a phase lead and a phase lag; pulse generating means for generating a pulse signal having pulses a number of which corresponds to the phase difference detected by said phase comparing means; counting means for incrementing or decrementing a value which is previously set, by said number of pulses in accordance with the discrimination between the phase lead and the phase lag which is detected by said phase comparing means; converting means for converting a count value of said counting means into a voltage corresponding to the count value, and feeding the voltage back to said voltage control oscillating means; and storage means for previously storing an initial value and setting the initial value to said counting means in response to a reset signal.

Claim 5

A PLL circuit comprising: phase comparing means for detecting a phase difference between a signal relating to an output of a voltage control oscillator and a reference signal, and discriminating between a phase lead and a phase lag; pulse generating means for generating a pulse signal having pulses a number of which corresponds to the phase difference detected by said phase comparing means; counting means for incrementing or decrementing a value which is previously set, by said number of pulses in accordance with the discrimination between the phase lead and a phase lag which is detected by said phase comparing means; converting means for converting a count value of said counting means into a voltage corresponding to the count value, and feeding the voltage back to said voltage control oscillator; storage means for storing a plurality of values which are to be set to said counting means; and means for selecting a desired value from said storage means, and setting the selected value to said counting means in response to a reset signal.

Claim 6

A PLL circuit comprising: phase comparing means for detecting a phase difference between a signal relating to an output of a voltage control oscillator and a reference signal, and discriminating between a phase lead and a phase lag; pulse generating means for generating a pulse signal having pulses a number of which corresponds to the phase difference detected by said phase comparing means; counting means for incrementing or decrementing a value which is previously set, by said number of pulses in accordance with the discrimination between the phase lead and a phase lag which is detected by said phase comparing means; converting means for converting a count value of said counting means into a voltage corresponding to the count value, and feeding the voltage back to said voltage control oscillator; storage means for storing a plurality of values which are to be set to said counting means; and means for selecting a desired value from said storage means, and setting the selected value to said counting means in response to a reset signal.

Claim 7

A PLL circuit according to claim 3, wherein said storage means comprises an initial register for previously storing an initial value which is set to said counting means, and a change register for storing as a change value a value other than the initial value.

Claim 8

A PLL circuit according to claim 4, wherein, in response to a reset signal, the initial value which is stored in said initial register is set to said counting means, and, in response to a control signal, the change value which is stored in said change register is set to said counting means.

Claim 9

A PLL circuit comprising: voltage control oscillating means for oscillating at a frequency corresponding to an input voltage; first frequency dividing means for dividing the oscillation frequency of said voltage control oscillating means; reference signal generating means for outputting a reference signal; second frequency dividing means for dividing an output frequency of said reference signal generating means, and outputting a plurality of frequency signals; selecting means for selecting a frequency signal corresponding to an objective oscillation frequency and functioning as a reference, from outputs of said second frequency dividing means; phase comparing means for detecting a phase difference between an output signal of said first frequency dividing means and an output signal of said selecting means, and discriminating between a phase lead and a phase lag; pulse generating means for generating a pulse signal having pulses a number of which corresponds to the phase difference detected by said phase comparing means; counting means for incrementing or decrementing a value which is previously set, by the number of pulses in accordance with the discrimination between the phase lead and the phase lag which is detected by said phase comparing means; converting means for converting a count value of said counting means into a voltage corresponding to the count value, and feeding the voltage back to said voltage control oscillating means; storage means for storing a plurality of values which are to be set to said counting means; and means for selecting a desired value from said storage means, and setting the selected value to said counting means in response to a reset signal.

Claim 10

A PLL circuit comprising: voltage control oscillating means for oscillating at a frequency corresponding to an input voltage; first frequency dividing means for dividing the oscillation frequency of said voltage control oscillating means; reference signal generating means for outputting a reference signal; second frequency dividing means for dividing an output frequency of said reference signal generating means, and outputting a plurality of frequency signals; selecting means for selecting a frequency signal corresponding to an objective oscillation frequency and functioning as a reference, from outputs of said second frequency dividing means; phase comparing means for detecting a phase difference between an output signal of said first frequency dividing means and an output signal of said selecting means, and discriminating between a phase lead and a phase lag; pulse generating means for generating a pulse signal having pulses a number of which corresponds to the phase difference detected by said phase comparing means; counting means for incrementing or decrementing a value which is previously set, by the number of pulses in accordance with the discrimination between the phase lead and the phase lag which is detected by said phase comparing means; converting means for converting a count value of said counting means into a voltage corresponding to the count value, and feeding the voltage back to said voltage control oscillating means; storage means for storing a plurality of values which are to be set to said counting means; and means for selecting a desired value from said storage means, and setting the selected value to said counting means in response to a reset signal.

Claim 11

A PLL circuit according to claim 6, wherein said storage means comprises an initial register for previously storing an initial value which is set to said counting means, and a change register for storing as a change value a value other than the initial value.

Claim 12

A PLL circuit according to claim 7, wherein, in response to a reset signal, a frequency signal corresponding to the initial value which is stored in said initial register and functioning as the reference is selected by said selecting means, and the initial value is set to said counting means, and, in response to a control signal, a frequency signal corresponding to the change value which is stored in said change register and functioning as the reference is selected by said selecting means, and the change value is set to said counting means.