Drift compensated phase lock loop

Claim 2

In a phase locked loop circuit having a crystal controlled oscillator which has a center operating frequency fc and output frequency fo, reference means which provide a reference frequency fr, first means, including phase comparator means connected to said reference means and to said oscillator for providing an output signal which represents the difference in the values of said frequency signals fr and fo, the improvement comprising compensation means, connected to the output of said first means, for receiving said output signal and for generating a frequency representative signal VF which initially represents the value of the center frequency fc of said oscillator, including means operative whenever said reference frequency is not present for holding the apparent center frequency of said oscillator to the last reference frequency known, and control means connected between said reference means and said compensation means, said control means being enabled whenever said reference frequency is present to selectively control said compensation means to adjust the value of said frequency representative signal to represent changes in the value of said center frequency fc of the crystal controlled oscillator.

Claim 3

A phase locked loop circuit as set forth in claim 1 which includes means for summing the frequency representative signal generated by said compensation means and the signal output of said first means for controlling said voltage controlled oscillator.

Claim 4

A phase locked loop circuit as set forth in claim 1 in which said first means provides a signal VV which indicates the difference between the frequency output fo of said voltage controlled oscillator and said reference frequency fr, and in which said compensation means includes summation means for adding said signals VV and VF to provide a summated signal VT to said voltage controlled oscillator.

Claim 5

A phase locked loOp as set forth in claim 3 in which said signal VV provided by said first means comprises a varying DC level signal, the value of which represents the difference in the frequencies fo and fr, and in which said compensation means comprises at least one reference signal, comparison means for comparing said signal VV with said one reference signal, and means for adjusting the value of said generated signal VF in accordance with the value of the output of said comparison means.

Claim 6

A phase locked loop circuit as set forth in claim 3 in which said compensation means include means for providing at least a first reference signal which represents a predetermined difference in phase of said frequency reference signal fr and said oscillator output frequency signal fo, and means operative to provide a K delta signal to said summation means for summing with said output signal, provided by said first means, whenever said output signal exceeds said first reference signal.

Claim 7

In a phase locked loop circuit, a crystal controlled oscillator which has a center operating frequency fc and output frequency fo, reference means which provide a reference frequency fr, and first means for providing an output signal VV which represents the difference in the values of said frequency signals fr and fo, compensation means connected to the output of said first means including second means responsive to said output signal for generating and storing a first signal which initially represents the value of the center frequency fc of said oscillator, and control means, connected to said reference means, including signal monitor means, for preventing operation of said second means during periods in which said reference frequency signal fr is absent, whereby the value of said first signal as stored is frozen in said second means, and means for deriving a signal from said stored signal for use with said output signal VV to control said oscillator.

Claim 8

In a phase locked loop circuit, a crystal controlled oscillator which has a center operating frequency fc and output frequency fo, reference means which provide a reference frequency fr, and first means for providing an output signal VV which represents the difference in the values of said frequency signals fr and fo, compensation means connected to the output of said first means including second means responsive to said output signal for generating and storing a first signal which initially represents the value of the center frequency fc of said oscillator, and control means, connected to said reference means, including signal monitor means, for preventing operation of said second means during periods in which said reference frequency signal fr is absent, whereby the value of said first signal as stored is frozen in said second means, and means for deriving a signal from said stored signal for use with said output signal VV to control said oscillator.

Claim 9

An improved phase locked loop of the type wherein a phase comparator, loop filter and crystal voltage controlled oscillator having a center frequency fc are loop connected to lock the phase of a signal output from said loop with the phase of a frequency reference signal fr, the improvement comprising: a. compensation means connected between said loop filter and said crystal voltage controlled oscillator operative to provide a compensating signal which represents changes in the frequency output of said oscillator due to variations in the oscillator center frequency characteristic, and b. control means for periodically enabling said compensation means to update said compensating signal to represent the changes which occur in said frequency output of said oscillator by reason of said variations.

Claim 10

An improved phase locked loop of the type wherein a phase comparator, loop filter and crystal voltage controlled oscillator having a center frequency fc are loop connected to lock the phase of a signal output from said loop with the phase of a frequency reference signal fr, the improvement comprising: a. compensation means connected between said loop filter and said crystal voltage controlled oscillator operative to provide a compensating signal which represents changes in the frequency output of said oscillator due to variations in the oscillator center frequency characteristic, and b. control means for periodically enabling said compensation means to update said compensating signal to represent the changes which occur in said frequency output of said oscillator by reason of said variations.

Claim 11

An improved phase locked loop as set forth in claim 7 wherein said compensation means further comprises: a. comparison means connected to said loop filter for providing a first signal whenever the value of the loop filter output signal exceeds the value of a first reference signal and a second signal whenever the value of said loop filter output is less than a second reference signal; b. signal generating means connected to said comparison means selectively enabled to be incremented and decremented responsive to said first and second signals respectively; and c. means for summing the output of said signal generating means with the output of said loop filter to produce a control voltage which is proportional to the difference between the reference input signal frequency fr and the actual center frequency fc to control said crystal voltage controlled oscillator.

Claim 12

An improved phase locked loop as set forth in claim 7 wherein said compensation means further comprises: a. first means connected to said loop filter to compare the outpuT of said loop filter with a first reference signal, and for generating a first signal whenever the value of the loop filter output signal exceeds the value of said first reference signal; b. second means connected to said loop filter to compare the output of said loop filter with a second reference signal, and for generating a second signal whenever said loop filter output fails to exceed said second reference signal; c. counter means connected to said first and second means having an increment input connected to said first means and a decrement input connected to said second means; d. means for selectively enabling said counter means to be responsive to the signals on said increment and decrement inputs at the time of enablement; e. conversion means for converting the count in said counter means into an analog signal, the magnitude of which is proportional to the count stored in said counter; f. means for summing the output of said conversion means with the output of said loop filter to produce a control voltage which is proportional to the difference between the reference input signal frequency fr and the actual center frequency fc of said crystal voltage controlled oscillator; and g. means for inputting said control voltage to said crystal voltage controlled oscillator.

Claim 13

An improved phase locked loop as in claim 7 wherein said control means further comprise a. an input circuit over which said input reference signal fr is input; b. a signal presence monitor means for generating a first output signal to represent the presence of a reference signal on said input circuit; c. clock means for periodically generating a second output signal; and d. means connected to said clock means and said signal presence monitor means for providing a third output signal responsive to simultaneous input of said first and second output signals; and e. means in said compensation means for updating said compensating signal in response to receipt of said third output signal.

Claim 14

An improved phase lock loop of the type wherein a phase comparator, loop filter and crystal voltage controlled oscillator having a center frequency are loop connected to lock the phase of the loop output signal to the phase of a reference signal received over an input circuit, the improvement comprising: a. first means connected to said loop filter for comparing the output of said loop filter with a first reference signal and for generating a first adjust signal whenever said loop filter exceeds the value of said first reference signal; b. second means connected to said loop filter output for comparing the output of said loop filter with a second reference signal, and for generating a second adjust signal whenever said loop filter output fails to exceed the value of said second reference signal; c. a signal presence monitor responsive to generate a third signal whenever said reference signal is applied to said input circuit; d. a clock for periodically generating a fourth signal; e. counter means connected to said first and second means to be incremented by one unit in response to input of one of said first adjust signals, and to be decremented in response to input of one of said second adjust signals; f. means responsive to said third and fourth signals connected to said counter means for periodically enabling said counter means to be responsive to the signals output by said first and second means; g. digital/analog means for converting the instantaneous digital value in said counter means into an analog signal having a magnitude which is proportional to the value in said counter; h. means for summing the output of said digital/analog means with the output of said loop filter to produce a control voltage proportional to the difference between said reference input signal frequency and the actual center frequency of said crystal voltage controlled oscillator; and means for inputting saiD control voltage to said crystal voltage controlled oscillator.

Claim 15

An improved phase lock loop of the type wherein a phase comparator, loop filter and crystal voltage controlled oscillator having a center frequency are loop connected to lock the phase of the loop output signal to the phase of a reference signal received over an input circuit, the improvement comprising: a. first means connected to said loop filter for comparing the output of said loop filter with a first reference signal and for generating a first adjust signal whenever said loop filter exceeds the value of said first reference signal; b. second means connected to said loop filter output for comparing the output of said loop filter with a second reference signal, and for generating a second adjust signal whenever said loop filter output fails to exceed the value of said second reference signal; c. a signal presence monitor responsive to generate a third signal whenever said reference signal is applied to said input circuit; d. a clock for periodically generating a fourth signal; e. counter means connected to said first and second means to be incremented by one unit in response to input of one of said first adjust signals, and to be decremented in response to input of one of said second adjust signals; f. means responsive to said third and fourth signals connected to said counter means for periodically enabling said counter means to be responsive to the signals output by said first and second means; g. digital/analog means for converting the instantaneous digital value in said counter means into an analog signal having a magnitude which is proportional to the value in said counter; h. means for summing the output of said digital/analog means with the output of said loop filter to produce a control voltage proportional to the difference between said reference input signal frequency and the actual center frequency of said crystal voltage controlled oscillator; and means for inputting saiD control voltage to said crystal voltage controlled oscillator.

Claim 16

An improved phase locked loop of the type wherein a phase comparator, loop filter and crystal voltage controlled oscillator having a center frequency fc are loop connected to lock the phase of the loop output signal to the phase of a reference signal which is received over an input circuit, the improvement comprising: a. first means connected to said loop filter for comparing the output of said loop filter with a first reference signal and for generating a first adjust signal whenever said loop filter exceeds the value of said first reference signal; b. second means connected to said loop filter for comparing the output of said loop filter with a second reference signal, and for generating a second adjust signal whenever said loop filter output fails to exceed the value of said second reference signal; c. a signal presence monitor responsive to generate a third signal whenever said reference signal is applied to said input circuit; d. clock means for periodically generating a fourth signal; e. counter means connected to said clock means to be periodically enabled by said third signal and incremented by one unit in response to simultaneous input of one of said first adjust signals and to be decremented in response to simultaneous input of one of said second adjust signals; f. conversion means for converting the count in said counter means into an analog signal having a magnitude which is proportional to the count in said counter; g. means for summing the output of said conversion means with the output of said loop filter to produce a control voltage VT which is proportional to the difference between said reference input signal frequency fr and the actual center frequency fc of said crystal voltage controlled oscillator; and h. means for coupling said control voltage to said crystal voltage controlled oscillator.

Claim 17

An improved phase locked loop of the type wherein a phase comparator, loop filter and crystal voltage controlled oscillator having a center frequency fc are loop connected to lock the phase of the loop output signal to the phase of a reference signal which is received over an input circuit, the improvement comprising: a. first means connected to said loop filter for comparing the output of said loop filter with a first reference signal and for generating a first adjust signal whenever said loop filter exceeds the value of said first reference signal; b. second means connected to said loop filter for comparing the output of said loop filter with a second reference signal, and for generating a second adjust signal whenever said loop filter output fails to exceed the value of said second reference signal; c. a signal presence monitor responsive to generate a third signal whenever said reference signal is applied to said input circuit; d. clock means for periodically generating a fourth signal; e. counter means connected to said clock means to be periodically enabled by said third signal and incremented by one unit in response to simultaneous input of one of said first adjust signals and to be decremented in response to simultaneous input of one of said second adjust signals; f. conversion means for converting the count in said counter means into an analog signal having a magnitude which is proportional to the count in said counter; g. means for summing the output of said conversion means with the output of said loop filter to produce a control voltage VT which is proportional to the difference between said reference input signal frequency fr and the actual center frequency fc of said crystal voltage controlled oscillator; and h. means for coupling said control voltage to said crystal voltage controlled oscillator.