US3573649A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frequency-lock circuit
Assignee: United States Department of the Navy
•
Filing: 1969-01-08
•
Granted: 1971-04-06
•
Expires: 1989-01-08
Abstract
Abstract A circuit for locking the frequency of an oscillator to that of a received signal. The latter is amplified, clipped and differentiated before being fed to a phase-lock loop comprising, in series, a phase comparator, low-pass filter, gating means, memory means and a voltage-controlled oscillator (VCO). The output of the VCO is fed back through a frequency divider to the phase comparator. The comparator produces a symmetrical output when the circuit input and output frequencies are equal and an unsymmetrical output when the frequencies differ. The unsymmetrical output provides a DC level when filtered, which is used to control the VCO frequency to bring it back to the input frequency after frequency division. The output of the frequency divider is also the output of the frequency-lock circuit.
Inventors
- 👤 Gerald W West
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 18:01
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/14; H03L7/16; H03L7/18
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
218 words
A frequency-lock circuit for locking the frequency of its output signal to the frequency of its input signal, comprising, in combination: input-signal processing means for providing an output signal whose frequency has a predetermined relation to the frequency of the input signal; and phase-lock loop means for providing an output signal identical in frequency to the frequency of its input signal, one input to said phase-lock loop means being the output signal of said input-signal processing means, said phasE-lock loop means comprising; phase comparison means having an output signal with a parameter whose value is proportional to the frequency of its input signal, memory means for storing the input signal of said phase comparison means, gating means for allowing the output signal of said phase comparison means to be fed to said memory means during a predetermined interval, and oscillator means for providing an output signal whose frequency is controlled by the value of the output signal of said memory means, the frequency of the output of the oscillator means being the same as the input frequency to said frequency-lock circuit when the output of said phase comparison circuit is zero, the output of said oscillator means being fed back to said phase comparison circuit as an input and being taken as the output of said frequency-lock circuit.
Claim 2
Dependent Claim
218 words
A frequency-lock circuit for locking the frequency of its output signal to the frequency of its input signal, comprising, in combination: input-signal processing means for providing an output signal whose frequency has a predetermined relation to the frequency of the input signal; and phase-lock loop means for providing an output signal identical in frequency to the frequency of its input signal, one input to said phase-lock loop means being the output signal of said input-signal processing means, said phasE-lock loop means comprising; phase comparison means having an output signal with a parameter whose value is proportional to the frequency of its input signal, memory means for storing the input signal of said phase comparison means, gating means for allowing the output signal of said phase comparison means to be fed to said memory means during a predetermined interval, and oscillator means for providing an output signal whose frequency is controlled by the value of the output signal of said memory means, the frequency of the output of the oscillator means being the same as the input frequency to said frequency-lock circuit when the output of said phase comparison circuit is zero, the output of said oscillator means being fed back to said phase comparison circuit as an input and being taken as the output of said frequency-lock circuit.
Claim 3
Dependent Claim
16 words
A circuit as set forth in claim 1, wherein phase comparison circuit comprises a sawtooth comparator.
Claim 4
Dependent Claim
65 words
A circuit as set forth in claim 1, wherein said input signal processing means comprises: an automatic-gain-control amplifier to which the input signal is applied; a clipping amplifier for clipping the output signal of said automatic-gain-control amplifier; and a differentiator for differentiating the output signal of said clipping amplifier, the output of said differentiator being fed as an input signal to said phase comparison means.
Claim 5
Dependent Claim
45 words
A circuit as set forth in claim 1, wherein said oscillator means comprises: a voltage-controlled oscillator connected to receive as an input the output of said gating means; and a frequency divider for dividing the frequency of the oscillator output signal by a predetermined amount.
Claim 6
Dependent Claim
53 words
A circuit as set forth in claim 1, wherein said gating means comprises: a gate circuit; and gate-enabling means for producing a gating signal for opening and closing said gate circuit as a switch, the duration of the gating signal being controlled by the duration of the input signal to said frequency-lock circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-04-05 | 1974-10-05 | 1975-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-04-05 | 1978-10-05 | 1979-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-04-05 | 1982-10-05 | 1983-04-06 | $7700.00 | Window Closed / Lapsed |