US5028885A
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Phase-locked loop signal generation system with control maintenance
Assignee: Motorola Solutions Inc
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Filing: 1990-08-30
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Granted: 1991-07-02
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Expires: 2010-08-30
Abstract
Abstract A phase-locked loop system having as input a stable refernce clock signal and outputting a master clock signal. The phase of the stable reference clock signal is compared to that of the pre-scaled master clock signal and the difference represented by an analog error signal which is converted to a digital signal by an A/D converter (116). The digital signal is then transformed into an analog control signal by a D/A converter (120) and applied to a VCO (128) which generates the master clock signal, If the stable reference clock signal has degraded or is lost the A/D converter (116), which receives its sampling clock in part from the stable reference clock signal, stops sampling and thus stops producing digital signals. The last good digital signal is maintained, the last good analog control signal is maintained and thus the master clock signal is maintained.
Inventors
- 👤 John Voigt
- 👤 Tom Kundmann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 01:27
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/14; H03L7/146; Y; Y10; Y10S; Y10S331/00; Y10S331/02
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
138 words
A phase-locked loop signal generation system having a stable reference clock signal input and outputting a master clock signal comprising: means for generating the master clock signal; means, coupled to the master clock signal and the stable reference clock signal, for producing an analog error signal; means, coupled to said means for producing and the stable reference clock signal, for converting said analog error signal to a digital signal; means, coupled to said means for converting, for transforming said digital signal to an analog control signal for coupling to said means for generating the master clock signal; means, coupled to said means for producing and said means for converting, for disabling said means for converting when the stable reference clock signal has degraded; and means for maintaining said digital signal when the stable reference clock signal has degraded.
Claim 2
Dependent Claim
138 words
A phase-locked loop signal generation system having a stable reference clock signal input and outputting a master clock signal comprising: means for generating the master clock signal; means, coupled to the master clock signal and the stable reference clock signal, for producing an analog error signal; means, coupled to said means for producing and the stable reference clock signal, for converting said analog error signal to a digital signal; means, coupled to said means for converting, for transforming said digital signal to an analog control signal for coupling to said means for generating the master clock signal; means, coupled to said means for producing and said means for converting, for disabling said means for converting when the stable reference clock signal has degraded; and means for maintaining said digital signal when the stable reference clock signal has degraded.
Claim 3
Dependent Claim
24 words
The phase-locked loop signal generation system of claim 1 wherein said means for generating the master clock signal further comprises a voltage controlled oscillator.
Claim 4
Dependent Claim
26 words
The phase-locked loop signal generation system of 1 wherein said means for disabling further comprises means for determining when the stable reference clock signal has degraded.
Claim 5
Dependent Claim
26 words
The phase-locked loop signal generation system of 1 wherein said means for disabling further comprises means for determining when the stable reference clock signal has degraded.
Claim 6
Dependent Claim
30 words
The phase-locked loop signal generation system of claim 1 wherein said means for producing further comprises means for generating an un-lock signal when the stable reference clock signal has degraded.
Claim 7
Dependent Claim
30 words
The phase-locked loop signal generation system of claim 1 wherein said means for producing further comprises means for generating a lock signal when the stable reference clock signal is present.
Claim 8
Dependent Claim
19 words
The phase-locked loop signal generation system of claim 1 wherein said means for disabling further comprises means for enabling.
Claim 9
Dependent Claim
27 words
The phase-locked loop signal generation system of claim 6 wherein said means for enabling enables said means for converting when the stable reference clock signal is present.
Claim 10
Dependent Claim
155 words
A digital radiotelephone system incorporating a phase-locked loop signal generation system having a stable reference clock signal input and outputting a master clock signal comprising: means for generating the master clock signal; means, coupled to the master clock signal and the stable reference clock signal, for producing an analog error signal; means, coupled to said means for producing and the stable reference clock signal, for converting said analog error signal to a digital signal; means, coupled to said means for converting, for transforming said digital signal to an analog control signal for coupling to said means for generating the master clock signal; means, coupled to said means for generating the master clock signal, for distributing the master clock signal; means, coupled to said means for distributing, for referencing to said master clock signal; and means, coupled to said means for referencing, for transmitting at least one radio frequency signal compatible to the digital radiotelephone system.
Claim 11
Dependent Claim
155 words
A digital radiotelephone system incorporating a phase-locked loop signal generation system having a stable reference clock signal input and outputting a master clock signal comprising: means for generating the master clock signal; means, coupled to the master clock signal and the stable reference clock signal, for producing an analog error signal; means, coupled to said means for producing and the stable reference clock signal, for converting said analog error signal to a digital signal; means, coupled to said means for converting, for transforming said digital signal to an analog control signal for coupling to said means for generating the master clock signal; means, coupled to said means for generating the master clock signal, for distributing the master clock signal; means, coupled to said means for distributing, for referencing to said master clock signal; and means, coupled to said means for referencing, for transmitting at least one radio frequency signal compatible to the digital radiotelephone system.
Claim 12
Dependent Claim
35 words
The digital radiotelephone system of claim 8 wherein said means for transmitting further comprises means for sustaining transmission of said at least one transmit radio frequency signal when the stable reference clock signal has degraded.
Claim 13
Dependent Claim
155 words
A digital radiotelephone system incorporating a phase-locked loop signal generation system having a stable reference clock signal input and outputting a master clock signal comprising: means for generating the master clock signal; means, coupled to the master clock signal and the stable reference clock signal, for producing an analog error signal; means, coupled to said means for producing and the stable reference clock signal, for converting said analog error signal to a digital signal; means, coupled to said means for converting, for transforming said digital signal to an analog control signal for coupling to said means for generating the master clock signal; means, coupled to said means for generating the master clock signal, for distributing the master clock signal; means, coupled to said means for distributing, for referencing to said master clock signal; and means, coupled to said means for referencing, for receiving at least one radio frequency signal compatible to the digital radiotelephone system.
Claim 14
Dependent Claim
155 words
A digital radiotelephone system incorporating a phase-locked loop signal generation system having a stable reference clock signal input and outputting a master clock signal comprising: means for generating the master clock signal; means, coupled to the master clock signal and the stable reference clock signal, for producing an analog error signal; means, coupled to said means for producing and the stable reference clock signal, for converting said analog error signal to a digital signal; means, coupled to said means for converting, for transforming said digital signal to an analog control signal for coupling to said means for generating the master clock signal; means, coupled to said means for generating the master clock signal, for distributing the master clock signal; means, coupled to said means for distributing, for referencing to said master clock signal; and means, coupled to said means for referencing, for receiving at least one radio frequency signal compatible to the digital radiotelephone system.
Claim 15
Dependent Claim
35 words
The digital radiotelephone system of claim 10 wherein said means for receiving further comprises means for sustaining reception of said at least one receive radio frequency signal when the stable reference clock signal has degraded.
Claim 16
Independent Claim
100 words
A method of stable signal generation in a phase-locked loop system having a stable reference clock signal input and outputting a master clock signal comprising the steps of: generating the master clock signal; producing an analog error signal from the master clock signal and the stable reference clock signal; converting said analog error signal to a digital signal; transforming said digital signal to an analog control signal for coupling to the master clock signal generator; disabling said step of converting when the stable reference clock signal has degraded; and maintaining said digital signal when the reference clock signal has degraded.
Claim 17
Independent Claim
100 words
A method of stable signal generation in a phase-locked loop system having a stable reference clock signal input and outputting a master clock signal comprising the steps of: generating the master clock signal; producing an analog error signal from the master clock signal and the stable reference clock signal; converting said analog error signal to a digital signal; transforming said digital signal to an analog control signal for coupling to the master clock signal generator; disabling said step of converting when the stable reference clock signal has degraded; and maintaining said digital signal when the reference clock signal has degraded.
Claim 18
Dependent Claim
24 words
The method of claim 12 wherein said step of disabling further comprises the step of determining when the stable reference clock signal has degraded.
Claim 19
Dependent Claim
27 words
The method of claim 12 wherein said step of producing further comprises the step of generating an un-lock signal when the stable reference clock signal has degraded.
Claim 20
Dependent Claim
27 words
The method of claim 12 wherein said step of producing further comprises the step of generating a lock signal when the stable reference clock signal is present.
Claim 21
Dependent Claim
16 words
The method of claim 12 wherein said step of disabling further comprises the step of enabling.
Claim 22
Dependent Claim
23 words
The method of claim 16 wherein said step of enabling enables said step of converting when the stable reference clock signal is present.
Claim 23
Independent Claim
117 words
A method of radio frequency signal communication in a digital radiotelephone system incorporating a phase-locked loop signal generation system having a stable reference clock signal input and outputting a master clock signal comprising the steps of: generating the master clock signal; producing an analog error signal from the master clock signal and the stable reference clock signal; converting said analog error signal to a digital signal; transforming said digital signal to an analog control signal for coupling to the master clock signal generator; distributing the master clock signal; referencing to the distributed master clock signal; and transmitting, employing the master clock signal as a reference, at least one radio frequency signal compatible to the digital radiotelephone system.
Claim 24
Independent Claim
117 words
A method of radio frequency signal communication in a digital radiotelephone system incorporating a phase-locked loop signal generation system having a stable reference clock signal input and outputting a master clock signal comprising the steps of: generating the master clock signal; producing an analog error signal from the master clock signal and the stable reference clock signal; converting said analog error signal to a digital signal; transforming said digital signal to an analog control signal for coupling to the master clock signal generator; distributing the master clock signal; referencing to the distributed master clock signal; and transmitting, employing the master clock signal as a reference, at least one radio frequency signal compatible to the digital radiotelephone system.
Claim 25
Dependent Claim
33 words
The method of claim 18 wherein said step of transmitting further comprises the step of sustaining transmission of said at least one radio frequency signal when the stable reference clock signal has degraded.
Claim 26
Independent Claim
117 words
A method of radio frequency signal communication in a digital radiotelephone system incorporating a phase-locked loop signal generation system having a stable reference clock signal input and outputting a master clock signal comprising the steps of: generating the master clock signal; producing an analog error signal from the master clock signal and the stable reference clock signal; converting said analog error signal to a digital signal; transforming said digital signal to an analog control signal for coupling to the master clock signal generator; distributing the master clock signal; referencing to the distributed master clock signal; and receiving, employing the master clock signal as a reference, at least one radio frequency signal compatible to the digital radiotelephone system.
Claim 27
Independent Claim
117 words
A method of radio frequency signal communication in a digital radiotelephone system incorporating a phase-locked loop signal generation system having a stable reference clock signal input and outputting a master clock signal comprising the steps of: generating the master clock signal; producing an analog error signal from the master clock signal and the stable reference clock signal; converting said analog error signal to a digital signal; transforming said digital signal to an analog control signal for coupling to the master clock signal generator; distributing the master clock signal; referencing to the distributed master clock signal; and receiving, employing the master clock signal as a reference, at least one radio frequency signal compatible to the digital radiotelephone system.
Claim 28
Dependent Claim
34 words
The method of claim 20 wherein said step of receiving further comprises the step of sustaining reception of said at least one receive radio frequency signal when the stable reference clock signal has degraded.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-01 | 1994-12-31 | 1995-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-01 | 1998-12-31 | 1999-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-01 | 2002-12-31 | 2003-07-02 | $7700.00 | Window Closed / Lapsed |