Microprocessor controlled phase locked loops

Claim 2

In a control system in which a digital counter is phase-locked to a reference frequency, an improvement comprising a processing unit connected to said digital counter for controlling the rate at which said counter counts; said reference frequency being divided into cycles and connected to said processing unit such that said processing unit can sense the start of a cycle, the half cycle point and the end of a cycle of said reference frequency; the most significant bit output of said counter being connected to said processing unit; said processing unit causing said counter to clear at the end of each cycle; and said processing unit sensing the output of said most significant bit at the half cycle point, and causing said counter to increase its rate of count if the output of the most significant bit is digital zero and causing said counter to decrease its rate of count if the most significant bit is a digital one.

Claim 3

In a control system as set forth in claim 1 further comprising a voltage controlled oscillator connected between said processing unit and said counter; the rate of the counter being controlled in accordance with frequency of the output of the voltage controlled oscillator; and the frequency of the output of the voltage controlled oscillator being controlled up or down by the processing unit in accordance with the output of the most significant bit at the half cycle point.

Claim 4

In a control system as set forth in claim 2 further comprising a digital to analog converter connected between said processing unit and said voltage controlled oscillator.

Claim 5

In a control system in which each of a plurality of digital counters is phase-locked to one of a corresponding plurality of reference frequencies, an improvement comprising a processing unit connected to said plurality of digital counters for controlling the rate at which each counter counts; each reference frequency being divided into cycles and connected to said processing unit such that said processing unit can sense the start of a cycle, the half cycle point and the end of a cycle of each reference frequency; the most significant bit output of each counter being connected to said processing unit; said processing unit causing each counter to clear at the end of each cycle of its corresponding reference frequency; and said processing unit sensing the output of said most significant bit of each counter at the half cycle point of its corresponding reference frequency, and causing each counter to increase its rate of count if the output of its most significant bit is digital zero and causing each counter to decrease its rate of count if its most significant bit is a digital one.

Claim 6

In a control system in which each of a plurality of digital counters is phase-locked to one of a corresponding plurality of reference frequencies, an improvement comprising a processing unit connected to said plurality of digital counters for controlling the rate at which each counter counts; each reference frequency being divided into cycles and connected to said processing unit such that said processing unit can sense the start of a cycle, the half cycle point and the end of a cycle of each reference frequency; the most significant bit output of each counter being connected to said processing unit; said processing unit causing each counter to clear at the end of each cycle of its corresponding reference frequency; and said processing unit sensing the output of said most significant bit of each counter at the half cycle point of its corresponding reference frequency, and causing each counter to increase its rate of count if the output of its most significant bit is digital zero and causing each counter to decrease its rate of count if its most significant bit is a digital one.

Claim 7

In a control system as set forth in claim 4 wherein said processing unit is divided into first and second parts; said first part being connected to said reference frequencies and to said counters; said first part being connected to said second part so as to allow said second part to sense when the half cycle point of a cycle of each reference frequency has occurred; and the most significant bit of each counter being connected to said second part for adjustment of the rate at which each counter counts so as to cause each counter to have a maximum count under steady state conditions when its associated reference frequency reaches the end of a cycle.