Field effect transistor with an improved Schottky gate structure

Claim 2

A Schottky barrier structure comprising: a Schottky gate electrode; a first layer in contact with said Schottky gate electrode, said first layer being made of a first compound semiconductor which is undoped, and said first layer having a thickness in the range of 5-10 nanometers; a second layer in contact with said first layer, said second layer being made of a second compound semiconductor which is undoped and which has a higher conduction band edge than a conduction band edge of said first compound semiconductor; a third layer in contact with said second layer, said third layer being made of a third compound semiconductor which is undoped and which has a smaller conduction band edge than a conduction band edge of said second compound semiconductor, said third layer having a thickness of not less than 20 nanometers; and a fourth layer in contact with said third layer, said fourth layer being made of a fourth compound semiconductor which is doped with an impurity.

Claim 3

The Schottky barrier structure as claimed in claim 1, wherein said first compound semiconductor comprises a compound semiconductor including In.

Claim 4

The Schottky barrier structure as claimed in claim 2, wherein said first compound semiconductor comprises InAlAs.

Claim 5

The Schottky barrier structure as claimed in claim 1, wherein said second compound semiconductor comprises AlAs.

Claim 6

The Schottky barrier structure as claimed in claim 1, wherein said second compound semiconductor comprises GaAs.

Claim 7

The Schottky barrier structure as claimed in claim 1, wherein said second compound semiconductor comprises GaP.

Claim 8

The Schottky barrier structure as claimed in claim 1, wherein said second compound semiconductor comprises In X Al 1-X As (0<X<0.4).

Claim 9

The Schottky barrier structure as claimed in claim 1, wherein said second compound semiconductor comprises Al X Ga 1-X As (0<X<1).

Claim 10

The Schottky barrier structure as claimed in claim 1, wherein said second compound semiconductor comprises Al X Ga 1-X P (0<X<1).

Claim 11

The Schottky barrier structure as claimed in claim 1, wherein said second compound semiconductor comprises GaAs Y P 1-Y (0<Y<1).

Claim 12

The Schottky barrier structure as claimed in claim 1, wherein said second compound semiconductor comprises AlAs 1-Y P Y (0<Y<1).

Claim 13

The Schottky barrier structure as claimed in claim 1, wherein said second compound semiconductor comprises Al X Ga 1-X As 1-Y P Y (0<X<1, 0<Y<1).

Claim 14

The Schottky barrier structure as claimed in claim 1, wherein said second compound semiconductor comprises Al X In 1-X As 1-Y P Y (0<X<1, 0<Y<1, 0.48<X+Y<2).

Claim 15

The Schottky barrier structure as claimed in claim 1, wherein said second layer has a thickness of 5 nanometers.

Claim 16

The Schottky barrier structure as claimed in claim 1, wherein said third layer is made of the same material as said first compound semiconductor.

Claim 17

The Schottky barrier structure as claimed in claim 1, further comprising: fifth and sixth layers sandwiched between said second layer and said third layer, wherein said fifth layer is in contact with said second layer and is made of the same material as said first compound semiconductor; and wherein said sixth layer is in contact with said third layer and is made of the same material as said second compound semiconductor.

Claim 18

The Schottky barrier structure as claimed in claim 1, wherein said fourth layer is doped with Si at a doping concentration of 2×10 18 cm -3 .

Claim 19

A Schottky gate field effect transistor comprising: a semiconductor substrate; a first layer formed on said semiconductor substrate and said first layer being made of a first compound semiconductor; a second layer formed on said first layer and said second layer being made of a second compound semiconductor having a higher conduction band edge than a conduction band edge of said first compound semiconductor, said second layer being undoped and having a thickness of not less than 20 nanometers; a third layer formed on said second layer and said third layer including at least one electron barrier layer made of a third compound semiconductor having a higher conduction band edge than said conduction band edge of said second compound semiconductor, said third layer being undoped and having a thickness in the range of 5-10 nanometers; a fourth layer formed on said third layer and said fourth layer being made of a fourth compound semiconductor having a lower conduction band edge than said conduction band edge of said third compound semiconductor; source and drain regions separated through a recess portion from one another and formed on said fourth layer and said source and drain regions being made of a fifth compound semiconductor having a lower conduction band edge than said conduction band edge of said fourth compound semiconductor; source and drain electrodes provided on said source and drain regions; and a Schottky gate electrode provided on an exposed surface of said fourth layer in said recess portion.

Claim 20

A Schottky gate field effect transistor comprising: a semiconductor substrate; a first layer formed on said semiconductor substrate and said first layer being made of a first compound semiconductor; a second layer formed on said first layer and said second layer being made of a second compound semiconductor having a higher conduction band edge than a conduction band edge of said first compound semiconductor, said second layer being undoped and having a thickness of not less than 20 nanometers; a third layer formed on said second layer and said third layer including at least one electron barrier layer made of a third compound semiconductor having a higher conduction band edge than said conduction band edge of said second compound semiconductor, said third layer being undoped and having a thickness in the range of 5-10 nanometers; a fourth layer formed on said third layer and said fourth layer being made of a fourth compound semiconductor having a lower conduction band edge than said conduction band edge of said third compound semiconductor; source and drain regions separated through a recess portion from one another and formed on said fourth layer and said source and drain regions being made of a fifth compound semiconductor having a lower conduction band edge than said conduction band edge of said fourth compound semiconductor; source and drain electrodes provided on said source and drain regions; and a Schottky gate electrode provided on an exposed surface of said fourth layer in said recess portion.

Claim 21

The Schottky gate field effect transistor as claimed in claim 18, wherein said third layer comprises dual electron barrier layers sandwiching a fifth layer made of a fifth compound semiconductor having a higher conduction band edge than said conduction band edge of said third compound semiconductor.

Claim 22

The Schottky gate field effect transistor as claimed in claim 18, wherein said fourth compound semiconductor comprises a compound semiconductor including In.

Claim 23

The Schottky gate field effect transistor as claimed in claim 20, wherein said fourth compound semiconductor comprises InAlAs.

Claim 24

The Schottky gate field effect transistor as claimed in claim 18, wherein said fourth compound semiconductor comprises a compound semiconductor including GaAs.

Claim 25

The Schottky gate filed effect transistor as claimed in claim 18, wherein said third compound semiconductor comprises AlAs.

Claim 26

The Schottky gate field effect transistor as claimed in claim 18, wherein said third compound semiconductor comprises GaAs.

Claim 27

The Schottky gate field effect transistor as claimed in claim 18, wherein said third compound semiconductor comprises GaP.

Claim 28

The Schottky gate field effect transistor as claimed in claim 18, wherein said third compound semiconductor comprises In X Al 1-X As (0<X<0.4).

Claim 29

The Schottky gate field effect transistor as claimed in claim 18, wherein said third compound semiconductor comprises Al X Ga 1-X As (0<X<1).

Claim 30

The Schottky gate field effect transistor as claimed in claim 18, wherein said third compound semiconductor comprises Al X Ga 1-X P (0<X<1).

Claim 31

The Schottky gate field effect transistor as claimed in claim 18, wherein said third compound semiconductor comprises GaAs Y P 1-Y (0<Y<1).

Claim 32

The Schottky gate field effect transistor as claimed in claim 18, wherein said third compound semiconductor comprises AlAs 1-Y P Y (0<Y<1).

Claim 33

The Schottky gate field effect transistor as claimed in claim 18, wherein said third compound semiconductor comprises Al X Ga 1-X As 1-Y P Y (0X<1, 0<Y<1).

Claim 34

The Schottky gate field effect transistor as claimed in claim 18, wherein said third compound semiconductor comprises Al X In 1-X As 1-Y P Y (0<X<1, 0<Y<1, 0.48<X+Y<2).

Claim 35

The Schottky gate field effect transistor as claimed in claim 18, wherein said electron barrier layer has a thickness of 5 nanometers.

Claim 36

The Schottky gate field effect transistor as claimed in claim 18, wherein said semiconductor substrate is made of a semi-insulating InP.

Claim 37

The Schottky gate field effect transistor as claimed in claim 18, wherein said semiconductor substrate is made of a semi-insulating GaAs.

Claim 38

The Schottky gate field effect transistor as claimed in claim 18, wherein said semiconductor substrate is made of silicon.

Claim 39

The Schottky gate field effect transistor as claimed in claim 19, wherein said fifth layer is made of InAlAs.

Claim 40

The Schottky gate field effect transistor as claimed in claim 19, wherein said fifth layer is made of AlGaAs.

Claim 41

The Schottky gate field effect transistor as claimed in claim 19, wherein said fifth layer has a thickness of 5 nanometers.

Claim 42

The Schottky gate field effect transistor as claimed in claim 18, wherein said second layer comprises: an undoped InAlAs layer having a thickness of 3 nanometers formed on said first layer; a Si-doped InAlAs layer having a thickness of 10 nanometers formed on said undoped InAlAs layer; and an undoped InAlAs layer having a thickness of 20 nanometers formed on said Si-doped InAlAs layer.

Claim 43

The Schottky gate field effect transistor as claimed in claim 18, wherein said second layer comprises an undoped AlGaAs layer having a thickness of 20 nanometers formed on said first layer.

Claim 44

The Schottky gate field effect transistor as claimed in claim 18, wherein said source and drain regions are made of a Si-doped InGaAs having an impurity concentration of 6×10 18 cm -3 .

Claim 45

The Schottky gate field effect transistor as claimed in claim 18, wherein said source and drain regions are made of an n-doped GaAs having an impurity concentration of 6×10 18 cm -3 .

Claim 46

The Schottky gate field effect transistor as claimed in claim 18, further comprising an undoped InAlAs buffer layer having a thickness of 300 nanometers formed between said semiconductor substrate and said first layer.

Claim 47

The Schottky gate field effect transistor as claimed in claim 18, wherein said first layer comprises a Si-doped InGaAs having an impurity concentration of 2×10 18 cm -3 .

Claim 48

The Schottky gate field effect transistor as claimed in claim 18, wherein said first layer comprises a Si-doped AlGaAs having an impurity concentration of 2×10 18 cm -3 .

Claim 49

The Schottky gate field effect transistor as claimed in claim 18, further comprising an undoped GaAs buffer layer having a thickness in the range of from 400 nanometers to 800 nanometers formed between said semiconductor substrate and said first layer.

Claim 50

The Schottky gate field effect transistor as claimed in claim 47, further comprising an undoped Al 0 .2 Ga 0 .8 As spacer layer having a thickness of 3 nanometers formed between said buffer layer and said first layer.