Pseudomorphic MODFET structure having improved linear power performance at microwave frequencies

Claim 2

In an HEMT semiconductor device structure having at least a substrate, a buffer layer formed on one side of the substrate, an InGaAs channel layer situated on a side of the buffer layer opposite from the substrate, a carrier supply layer formed on one side of the channel layer opposite the buffer layer, an ohmic contact layer situated on a side of the carrier supply layer opposite from the InGaAs channel layer, a source contact formed on a surface of the ohmic contact layer opposite from the carrier supply layer, a drain contact formed on the surface of the ohmic contact layer at a distance from the source contact, and a gate contact formed through an opening in the ohmic contact layer, the improvement comprising the carrier supply layer consisting of a higher carrier mobility and velocity material than n+ AlGaAs and n+ AlInAs.

Claim 3

The improved HEMT semiconductor device structure of claim 1 wherein the carrier supply layer consists of n+ GaAs material.

Claim 4

The improved HEMT semiconductor device structure of claim 1 wherein the carrier supply layer consists of a material selected from among a group of materials comprising n GaAs, n and n+ In x Ga 1-x As, and n and n+ InP material.

Claim 5

A high gain and high linear power HEMT semiconductor device structure comprising: a substrate having a first surface and a second surface; a buffer layer having a first surface and a second surface, the buffer layer being formed on the substrate with the first surface of the buffer layer in contact with the second surface of the substrate; an InGaAs channel layer having a first surface and a second surface, the channel layer being situated above the second surface of the buffer layer; a carrier supply layer having a first surface and a second surface, the carrier supply layer consisting of n+ GaAs material, the carrier supply layer being situated above the second surface of the channel layer; an ohmic contact layer having a first surface and a second surface, the ohmic contact layer being situated above the second surface of the carrier supply layer; a source contact formed on the second surface of the ohmic contact layer; a drain contact formed on the second surface of the ohmic contact layer at a distance from the source contact; and a gate contact formed through an opening in the ohmic contact layer.

Claim 6

A high gain and high linear power HEMT semiconductor device structure comprising: a substrate having a first surface and a second surface; a buffer layer having a first surface and a second surface, the buffer layer being formed on the substrate with the first surface of the buffer layer in contact with the second surface of the substrate; an InGaAs channel layer having a first surface and a second surface, the channel layer being situated above the second surface of the buffer layer; a carrier supply layer having a first surface and a second surface, the carrier supply layer consisting of n+ GaAs material, the carrier supply layer being situated above the second surface of the channel layer; an ohmic contact layer having a first surface and a second surface, the ohmic contact layer being situated above the second surface of the carrier supply layer; a source contact formed on the second surface of the ohmic contact layer; a drain contact formed on the second surface of the ohmic contact layer at a distance from the source contact; and a gate contact formed through an opening in the ohmic contact layer.

Claim 7

The high gain and high linear power HEMT semiconductor device structure of claim 4 wherein the substrate consists of semi-insulating GaAs material.

Claim 8

The high gain and high linear power HEMT semiconductor device structure of claim 4 wherein the substrate consists of InP material.

Claim 9

The high gain and high linear power HEMT semiconductor device structure of claim 5 wherein the substrate is approximately 10 to 12 mils thick.

Claim 10

The high gain and high linear power HEMT semiconductor device structure of claim 6 wherein the substrate is approximately 10 to 12 mils thick.

Claim 11

The high gain and high linear power HEMT semiconductor device structure of claim 4 wherein the buffer layer consists of intrinsic GaAs material.

Claim 12

The high gain and high linear power HEMT semiconductor device structure of claim 9 wherein the buffer layer has a thickness of approximately 5000 Angstroms.

Claim 13

The high gain and high linear power HEMT semiconductor device structure of claim 4 wherein the channel layer consists of intrinsic In 0 .25 Ga 0 .75 As material.

Claim 14

The high gain and high linear power HEMT semiconductor device structure of claim 11 wherein the channel layer has a thickness of approximately 150 Angstroms.

Claim 15

The high gain and high linear power HEMT semiconductor device structure of claim 4 wherein the carrier supply layer is doped to a concentration of 2.2×10 18 /cm 3 and has a thickness of approximately 100 Angstroms.

Claim 16

The high gain and high linear power HEMT semiconductor device structure of claim 4 wherein the ohmic contact layer consists of n+ GaAs material doped to a concentration of 2×10 18 /cm 3 and has a thickness of approximately 500 Angstroms.

Claim 17

The high gain and high linear power HEMT semiconductor device structure of claim 4, further comprising: a superlattice buffer layer having a first surface and a second surface, the superlattice buffer layer being formed on the buffer layer with the first surface of the superlattice buffer layer in contact with the second surface of the buffer layer; a second carrier supply layer having a first surface and a second surface, the second carrier supply layer being formed on the superlattice buffer layer with the first surface of the second carrier supply layer in contact with the second surface of the superlattice buffer layer so that the second carrier layer is intermediate the superlattice buffer layer and the channel layer; a GaAs spacer layer having a first surface and a second surface, the GaAs spacer layer being formed on the first carrier supply layer with the first surface of the GaAs spacer layer in contact with the second surface of the first carrier supply layer; and a Schottky gate layer having a first surface and a second surface, the Schottky gate layer being formed on the GaAs spacer layer with the first surface of the Schottky gate layer in contact with the second surface of the GaAs spacer layer; the ohmic contact layer being formed on the second surface of the Schottky gate layer with the first surface of the ohmic contact layer being in contact with the second surface of the Schottky gate layer, the Schottky gate layer forming an etch stop layer beneath the ohmic contact layer, metal being deposited through the opening in the ohmic contact layer onto the second surface of the Schottky gate layer to form the gate.

Claim 18

The high gain and high linear power HEMT semiconductor device structure of claim 15 wherein the superlattice buffer layer consists of GaAs/AlGaAs material, the second carrier supply layer consists of n+ AlGaAs material, and the Schottky gate layer consists of intrinsic AlGaAs material.

Claim 19

The high gain and high linear power HEMT semiconductor device structure of claim 16 wherein the superlattice buffer layer consists of a material selected from among the group of materials comprising intrinsic and slightly p- GaAs/Al 0 .28 Ga 0 .72 As material and has a thickness of approximately 1000 Angstroms, the second carrier supply layer consists of n+ Al 0 .28 Ga 0 .72 As material and has a thickness of approximately 50 Angstroms, the GaAs spacer layer is doped to a concentration of 4×10 16 cm 3 and has a thickness of approximately 170 Angstroms, and the Schottky gate layer consists of intrinsic Al 0 .28 Ga 0 .72 As material and has a thickness of approximately 100 Angstroms.

Claim 20

The high gain and high linear power HEMT semiconductor device structure of claim 15, further comprising: a second spacer layer having a first surface and a second surface, the second spacer layer being formed on the second surface of the second carrier supply layer with the first surface of the second spacer layer in contact with the second surface of the second carrier supply layer; the channel layer being formed on the second surface of the second spacer layer with the first surface of the channel layer being in contact with the second surface of the second spacer layer; and a third spacer layer having a first surface and a second surface, the third spacer layer being formed on the second surface of the channel layer with the first surface of the third spacer layer in contact with the second surface of the channel layer; the first carrier supply layer being formed on the second surface of the third spacer layer with the first surface of the first carrier layer being in contact with the second surface of the third spacer layer.

Claim 21

The high gain and high linear power HEMT semiconductor device structure of claim 18 wherein the second spacer layer consists of intrinsic AlGaAs material and the third spacer layer consists of a material selected from among the group of materials comprising intrinsic GaAs and intrinsic AlGaAs material.

Claim 22

The high gain and high linear power HEMT semiconductor device structure of claim 19 wherein the second spacer layer consists of intrinsic Al 0 .28 Ga 0 .72 As material and has a thickness of approximately 20 to 40 Angstroms and the third spacer layer consists of a material selected from among the group of materials comprising intrinsic GaAs and intrinsic Al 0 .28 Ga 0 .72 As material and has a thickness of approximately 20 to 40 Angstroms.