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JPS6466972A Expired / Lapsed JP ⏱️ 0.0 years remaining

Heterojunction fet

Assignee: Fujitsu Ltd
•
Filing: 1987-09-07
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Granted: —
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Expires: 2007-09-07
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Abstract

Abstract PURPOSE:To prevent electron mobility from being lowered at a low temperature, by laminating a buffer layer, a channel layer, a distortion relaxation layer and a two-dimensional electron gas (2DEG) supplying layer sequentially on a semiconductor substrate and putting a gate electrode thereon to lattice matching between the channel layer and the distortion relaxation layer. CONSTITUTION:A undoped GaAs layer of 1mum as a buffer layer 11, a undoped InxGa1-xAs(x=0.15) layer 150A as a channel layer 12, a non-doped InxAl1-xAs(k=0.15) layer 20A as a distortion relaxation layer 13 and an Si doped (1.5X10<18> cm<-3>) AlxGa1-xAs(x=0.15) layer 300A as a 2DEG supplying layer 14 are sequentially superposed on a GaAs substrate 10 and a gate electrode 1b is put thereon. Electron mobility of 77K is improved because of the distortion relaxation layer.

Inventors

  • 👤 Tatsuya Ohori

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 09:58
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/473

Claims Analysis

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References Cited (Backward Citations)

JPS6012775A Cited
JPS613464A Cited
JPS6123364A Cited
JPS61110469A Cited

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