Method of making semiconductor device with floating bate

Claim 2

A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said main surface of said semiconductor substrate and spaced from each other by a distance with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of: forming a first insulating layer having a first thickness and formed at least on that region of said main surface of said semiconductor substrate on which said channel region is formed; forming a second insulating layer having a second thickness larger than said first thickness at least on a region, on which one of said impurity regions is formed, of said main surface of said semiconductor substrate; forming a charge accumulating electrode layer on said first insulating layer and said second insulating layer; forming a control electrode layer on said charge accumulating electrode layer with a third insulating layer therebetween; patterning said control electrode layer, said third insulating layer, said charge accumulating electrode layer and said second insulating layer to form said control electrode and said charge accumulating electrode; and implanting impurity into said semiconductor substrate, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.

Claim 3

A manufacturing method of a semiconductor memory device according to claim 1, wherein said step of forming said second insulating layer includes the step of forming said second insulating layer to surround said first insulating layer.

Claim 4

A manufacturing method of a semiconductor memory device according to claim 1, wherein said step of forming said second insulating layer includes the step of forming said second insulating film which has a tapered shape of which thickness reduces toward said channel region.

Claim 5

A manufacturing method of a semiconductor memory device according to claim 1, wherein said second insulating film is formed of a first film for preventing entry of oxidizer and a second film for improving an adherence between said first film and at least one of said charge accumulating electrode and said semiconductor substrate.

Claim 6

A manufacturing method of a semiconductor memory device according to claim 1, wherein said second insulating layer includes at least one film selected from the group consisting of a nitride film, and a CVD oxide film or a thermal oxide film.

Claim 7

A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said semiconductor substrate with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of: forming a first insulating layer at least on that region of said main surface of said semiconductor substrate on which said channel region is formed; forming an oxidizer entry preventing layer for intercepting passage of electrons between said charge storage electrode and said pair of impurity regions at the time of writing and erasing of information and for preventing entrance of oxidizer at least on a region on which one of said impurity regions is formed, of said main surface of said semiconductor substrate; forming said charge accumulating electrode layer on said first insulating layer and said oxidizer entry preventing layer; forming said control electrode layer on said charge accumulating electrode layer with a second insulating layer therebetween; patterning said control electrode layer, said second insulating layer, said charge accumulating electrode layer and said oxidizer entry preventing layer to form said control electrode and said charge accumulating electrode; and implanting impurity into said semiconductor substrate, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.

Claim 8

A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said semiconductor substrate with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of: forming a first insulating layer at least on that region of said main surface of said semiconductor substrate on which said channel region is formed; forming an oxidizer entry preventing layer for intercepting passage of electrons between said charge storage electrode and said pair of impurity regions at the time of writing and erasing of information and for preventing entrance of oxidizer at least on a region on which one of said impurity regions is formed, of said main surface of said semiconductor substrate; forming said charge accumulating electrode layer on said first insulating layer and said oxidizer entry preventing layer; forming said control electrode layer on said charge accumulating electrode layer with a second insulating layer therebetween; patterning said control electrode layer, said second insulating layer, said charge accumulating electrode layer and said oxidizer entry preventing layer to form said control electrode and said charge accumulating electrode; and implanting impurity into said semiconductor substrate, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.

Claim 9

A manufacturing method of a semiconductor memory device according to claim 6, wherein said step of forming said oxidizer entry preventing layer includes the step of forming said oxidizer entry preventing layer to surround said first insulating layer.

Claim 10

A manufacturing method of a semiconductor memory device according to claim 6, wherein said oxidizer entry preventing layer has a thickness larger than that of said first insulating layer.

Claim 11

A manufacturing method of a semiconductor memory device according to claim 6, wherein said oxidizer entry preventing layer has a tapered shape of which thickness reduces toward said channel region.

Claim 12

A manufacturing method of a semiconductor memory device according to claim 4, wherein said oxidizer entry preventing layer includes at least one film selected from the group consisting of a nitride film and a thermal oxide film.

Claim 13

A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said main surface of said semiconductor substrate and spaced from each other by a distance with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of: forming a first insulating layer having a first thickness at least on a first region on which one of said impurity regions is to be formed in said main surface of said semiconductor substrate; forming a second insulating layer having a second thickness smaller than the first thickness and formed at least on a second region of said main surface of said semiconductor substrate on which said channel region is formed, said second insulating layer being of a different material than said first insulating layer; forming a charge accumulating electrode layer on said first insulating layer and said second insulating layer; forming a control electrode layer on said charge accumulating electrode layer with a third insulating layer therebetween; patterning said control electrode layer, said third insulating layer, said charge accumulating electrode layer and said second insulating layer to form said control electrode and said charge accumulating electrode; and implanting impurity into said semiconductor substrate, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.

Claim 14

A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said main surface of said semiconductor substrate and spaced from each other by a distance with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of: forming a first insulating layer having a first thickness at least on a first region on which one of said impurity regions is to be formed in said main surface of said semiconductor substrate; forming a second insulating layer having a second thickness smaller than the first thickness and formed at least on a second region of said main surface of said semiconductor substrate on which said channel region is formed, said second insulating layer being of a different material than said first insulating layer; forming a charge accumulating electrode layer on said first insulating layer and said second insulating layer; forming a control electrode layer on said charge accumulating electrode layer with a third insulating layer therebetween; patterning said control electrode layer, said third insulating layer, said charge accumulating electrode layer and said second insulating layer to form said control electrode and said charge accumulating electrode; and implanting impurity into said semiconductor substrate, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.

Claim 15

A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said main surface of said semiconductor substrate and spaced from each other by a distance with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of: forming a first insulating layer having a first thickness at least on a first region on which one of said impurity regions is to be formed in said main surface of said semiconductor substrate; forming a second insulating layer having a second thickness smaller than the first thickness and formed at least on a second region of said main surface of said semiconductor substrate on which said channel region is formed, said second insulating layer being separately formed as a separate process step than said step of forming said first insulating layer; forming a charge accumulating electrode layer on said first insulating layer and said second insulating layer; forming a control electrode layer on said charge accumulating electrode layer with a third insulating layer therebetween; patterning said control electrode layer, said third insulating layer, said charge accumulating electrode layer and said second insulating layer to form said control electrode and said charge accumulating electrode; and implanting impurity into said semiconductor substrate, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.

Claim 16

A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said main surface of said semiconductor substrate and spaced from each other by a distance with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of: forming a first insulating layer having a first thickness at least on a first region on which one of said impurity regions is to be formed in said main surface of said semiconductor substrate; forming a second insulating layer having a second thickness smaller than the first thickness and formed at least on a second region of said main surface of said semiconductor substrate on which said channel region is formed, said second insulating layer being separately formed as a separate process step than said step of forming said first insulating layer; forming a charge accumulating electrode layer on said first insulating layer and said second insulating layer; forming a control electrode layer on said charge accumulating electrode layer with a third insulating layer therebetween; patterning said control electrode layer, said third insulating layer, said charge accumulating electrode layer and said second insulating layer to form said control electrode and said charge accumulating electrode; and implanting impurity into said semiconductor substrate, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.

Claim 17

A manufacturing method of a semiconductor memory device according to claim 12, wherein said step of forming said second insulating layer further comprises the step of forming said second insulating layer of a different material than said first insulating layer.

Claim 18

A manufacturing method of a semiconductor memory device according to claim 13, wherein said step of implanting impurity into said semiconductor substrate further comprises the step of implanting impurity into said semiconductor substrate only after said step of patterning said control electrode layer, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.

Claim 19

A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said main surface of said semiconductor substrate and spaced from each other by a distance with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of: forming a first insulating layer having a first thickness at least on a first region on which one of said impurity regions is to be formed in said main surface of said semiconductor substrate; forming a second insulating layer having a second thickness smaller than the first thickness and formed at least on a second region of said main surface of said semiconductor substrate on which said channel region is formed, said second insulating layer being of a different material than said first insulating layer; forming a charge accumulating electrode layer on said first insulating layer and said second insulating layer; forming a control electrode layer on said charge accumulating electrode layer with a third insulating layer therebetween; patterning said control electrode layer, said third insulating layer, said charge accumulating electrode layer and said second insulating layer to form said control electrode and said charge accumulating electrode; and implanting impurity into said semiconductor substrate only after said step of patterning said control electrode layer, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.

Claim 20

A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said main surface of said semiconductor substrate and spaced from each other by a distance with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of: forming a first insulating layer having a first thickness at least on a first region on which one of said impurity regions is to be formed in said main surface of said semiconductor substrate; forming a second insulating layer having a second thickness smaller than the first thickness and formed at least on a second region of said main surface of said semiconductor substrate on which said channel region is formed, said second insulating layer being of a different material than said first insulating layer; forming a charge accumulating electrode layer on said first insulating layer and said second insulating layer; forming a control electrode layer on said charge accumulating electrode layer with a third insulating layer therebetween; patterning said control electrode layer, said third insulating layer, said charge accumulating electrode layer and said second insulating layer to form said control electrode and said charge accumulating electrode; and implanting impurity into said semiconductor substrate only after said step of patterning said control electrode layer, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.

Claim 21

A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said semiconductor substrate with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of: forming a first insulating layer at least on that region of said main surface of said semiconductor substrate on which said channel region is formed; forming an oxidizer entry preventing layer for intercepting passage of electrons between said charge storage electrode and said pair of impurity regions at the time of writing and erasing of information and for preventing entrance of oxidizer at least on a region on which one of said impurity regions is formed, of said main surface of said semiconductor substrate; forming said charge accumulating electrode layer on said first insulating layer and said oxidizer entry preventing layer; forming said control electrode layer on said charge accumulating electrode layer with a second insulating layer therebetween, said second insulating layer being of a different material than said first insulating layer; patterning said control electrode layer, said second insulating layer, said charge accumulating electrode layer and said oxidizer entry preventing layer to form said control electrode and said charge accumulating electrode; and implanting impurity into said semiconductor substrate, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.

Claim 22

A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said semiconductor substrate with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of: forming a first insulating layer at least on that region of said main surface of said semiconductor substrate on which said channel region is formed; forming an oxidizer entry preventing layer for intercepting passage of electrons between said charge storage electrode and said pair of impurity regions at the time of writing and erasing of information and for preventing entrance of oxidizer at least on a region on which one of said impurity regions is formed, of said main surface of said semiconductor substrate; forming said charge accumulating electrode layer on said first insulating layer and said oxidizer entry preventing layer; forming said control electrode layer on said charge accumulating electrode layer with a second insulating layer therebetween, said second insulating layer being of a different material than said first insulating layer; patterning said control electrode layer, said second insulating layer, said charge accumulating electrode layer and said oxidizer entry preventing layer to form said control electrode and said charge accumulating electrode; and implanting impurity into said semiconductor substrate, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.

Claim 23

A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said semiconductor substrate with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of: forming a first insulating layer at least on that region of said main surface of said semiconductor substrate on which said channel region is formed; forming an oxidizer entry preventing layer for intercepting passage of electrons between said charge storage electrode and said pair of impurity regions at the time of writing and erasing of information and for preventing entrance of oxidizer at least on a region on which one of said impurity regions is formed, of said main surface of said semiconductor substrate; forming said charge accumulating electrode layer on said first insulating layer and said oxidizer entry preventing layer; forming said control electrode layer on said charge accumulating electrode layer with a second insulating layer therebetween, said second insulating layer being separately formed as a separate process step than said step of forming said first insulating layer; patterning said control electrode layer, said second insulating layer, said charge accumulating electrode layer and said oxidizer entry preventing layer to form said control electrode and said charge accumulating electrode; and implanting impurity into said semiconductor substrate, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.

Claim 24

A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said semiconductor substrate with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of: forming a first insulating layer at least on that region of said main surface of said semiconductor substrate on which said channel region is formed; forming an oxidizer entry preventing layer for intercepting passage of electrons between said charge storage electrode and said pair of impurity regions at the time of writing and erasing of information and for preventing entrance of oxidizer at least on a region on which one of said impurity regions is formed, of said main surface of said semiconductor substrate; forming said charge accumulating electrode layer on said first insulating layer and said oxidizer entry preventing layer; forming said control electrode layer on said charge accumulating electrode layer with a second insulating layer therebetween, said second insulating layer being separately formed as a separate process step than said step of forming said first insulating layer; patterning said control electrode layer, said second insulating layer, said charge accumulating electrode layer and said oxidizer entry preventing layer to form said control electrode and said charge accumulating electrode; and implanting impurity into said semiconductor substrate, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.

Claim 25

A manufacturing method of a semiconductor memory device according to claim 17, wherein said step of forming said second insulating layer further comprises the step of forming said second insulating layer of a different material than said first insulating layer.

Claim 26

A manufacturing method of a semiconductor memory device according to claim 18, wherein said step of implanting impurity into said semiconductor substrate further comprises the step of implanting impurity into said semiconductor substrate only after said step of patterning said control electrode layer, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.

Claim 27

A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said semiconductor substrate with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of: forming a first insulating layer at least on that region of said main surface of said semiconductor substrate on which said channel region is formed; forming an oxidizer entry preventing layer for intercepting passage of electrons between said charge storage electrode and said pair of impurity regions at the time of writing and erasing of information and for preventing entrance of oxidizer at least on a region on which one of said impurity regions is formed, of said main surface of said semiconductor substrate; forming said charge accumulating electrode layer on said first insulating layer and said oxidizer entry preventing layer; forming said control electrode layer on said charge accumulating electrode layer with a second insulating layer therebetween, said second insulating layer being separately formed as a separate process step than said step of forming said first insulating layer; patterning said control electrode layer, said second insulating layer, said charge accumulating electrode layer and said oxidizer entry preventing layer to form said control electrode and said charge accumulating electrode; and implanting impurity into said semiconductor substrate only after said step of patterning said control electrode layer, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.

Claim 28

A manufacturing method of a semiconductor memory device including a semiconductor substrate of a first conductivity type having a main surface, a pair of impurity regions of a second conductivity type formed on said semiconductor substrate with a channel region therebetween, a charge accumulating electrode, and a control electrode, comprising the steps of: forming a first insulating layer at least on that region of said main surface of said semiconductor substrate on which said channel region is formed; forming an oxidizer entry preventing layer for intercepting passage of electrons between said charge storage electrode and said pair of impurity regions at the time of writing and erasing of information and for preventing entrance of oxidizer at least on a region on which one of said impurity regions is formed, of said main surface of said semiconductor substrate; forming said charge accumulating electrode layer on said first insulating layer and said oxidizer entry preventing layer; forming said control electrode layer on said charge accumulating electrode layer with a second insulating layer therebetween, said second insulating layer being separately formed as a separate process step than said step of forming said first insulating layer; patterning said control electrode layer, said second insulating layer, said charge accumulating electrode layer and said oxidizer entry preventing layer to form said control electrode and said charge accumulating electrode; and implanting impurity into said semiconductor substrate only after said step of patterning said control electrode layer, using said control electrode and said charge accumulating electrode as a mask, to form said pair of impurity regions of said second conductivity type.