EP0368097A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A cross-point contact-free floating-gate memory array with silicided buried bitlines
Assignee: Texas Instruments Inc
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Filing: 1989-10-27
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Granted: —
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Expires: 2009-10-27
Abstract
Abstract A contact-free floating-gate non-volatile memory cell array (1) and process with silicided NSAG bitlines (2,4) and with source/drain regions (SD) buried beneath relatively thick silicon oxide (5). The silicided bitlines (2,4) have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array (1) has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines (13) and between silicided bitlines (2,4) is by thick field oxide or by P/N junction or trench isolation. Wordlines (13) may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate (8) is improved by extending the gates (8) and (10) over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate (10) and the floating gate (8). The resulting structure is a dense cross-point array of programmable memory cells.
Inventors
- 👤 Manzur Gill
- 👤 David J. Mcelroy
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 13:45
CPC Classifications
H; H10; H10B; H10B69/00
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
271 words
A non-volatile memory cell array (1), comprising: a plurality of conductors (2) including source-drain regions (SD) formed in a face of a semiconductor substrate (3), each of said conductors (2) being a heavily-doped region of second conductivity-type opposite that of a first conductivity-type of the underlying material of said semiconductor substrate (3), each of said conductors (2) being buried under a relatively thick first insulating oxide strip (5) on said face, each of said source-drain regions (SD) being spaced from at least one other said source-drain region (SD) on said face by a channel area (C); oxide regions (6) located in the face of said semiconductor substrate between each pair of said conductors (2) and between each pair of said channel areas (C); a floating gate (8) over each said channel area, the floating gate (8) being separated from said channel area of said face by a gate oxide layer (4), wherein said floating gate (8) extends over a part of each adjacent thick field oxide region (6), the extensions being in directions substantially at right angles to the direction of said conductors (2); a control gate (10) extending along said face over said floating gate (8), the control gate (10) being separated from said floating gate (8) by an inter-level dielectric layer (11); and a plurality of wordlines (13) contacting said control gates (10) and extending over said control gates (10) and over said first insulating oxide strip (6) in a direction substantially at right angle to the direction of said conductors (2); wherein each of said conductors (2) including said source-drain regions (SD) also includes a silicided region (4).
Claim 2
Dependent Claim
271 words
A non-volatile memory cell array (1), comprising: a plurality of conductors (2) including source-drain regions (SD) formed in a face of a semiconductor substrate (3), each of said conductors (2) being a heavily-doped region of second conductivity-type opposite that of a first conductivity-type of the underlying material of said semiconductor substrate (3), each of said conductors (2) being buried under a relatively thick first insulating oxide strip (5) on said face, each of said source-drain regions (SD) being spaced from at least one other said source-drain region (SD) on said face by a channel area (C); oxide regions (6) located in the face of said semiconductor substrate between each pair of said conductors (2) and between each pair of said channel areas (C); a floating gate (8) over each said channel area, the floating gate (8) being separated from said channel area of said face by a gate oxide layer (4), wherein said floating gate (8) extends over a part of each adjacent thick field oxide region (6), the extensions being in directions substantially at right angles to the direction of said conductors (2); a control gate (10) extending along said face over said floating gate (8), the control gate (10) being separated from said floating gate (8) by an inter-level dielectric layer (11); and a plurality of wordlines (13) contacting said control gates (10) and extending over said control gates (10) and over said first insulating oxide strip (6) in a direction substantially at right angle to the direction of said conductors (2); wherein each of said conductors (2) including said source-drain regions (SD) also includes a silicided region (4).
Claim 3
Dependent Claim
38 words
A memory cell array (1) according to Claim 1 including channel stop regions (7) of the same conductivity-type as that of the underlying material of said semiconductor substrate (3), said channel stop regions underlying said oxide regions (6).
Claim 4
Dependent Claim
19 words
A memory cell array (1) according to Claim 1 wherein said oxide regions (6) are thick field oxide regions.
Claim 5
Dependent Claim
23 words
A memory cell array (1) according to Claim 1 wherein said oxide regions (6) are deposited oxide extending to said semiconductor substrate (3).
Claim 6
Dependent Claim
23 words
A memory cell array (1) according to Claim 1 wherein said oxide regions (6) are deposited oxide extending into said semiconductor substrate (3).
Claim 7
Dependent Claim
37 words
A memory cell array (1) according to Claim 1 including second insulating oxide strips (14) on said face between said wordlines and over portions of said first insulating oxide strips (4) and over said oxide regions (6).
Claim 8
Dependent Claim
28 words
A memory cell array (1) according to Claim 1 wherein said semiconductor substrate (3) is silicon, and said first conductivity-type is P-type and said second conductivity-type is N-type.
Claim 9
Dependent Claim
26 words
A memory cell array (1) according to Claim 1 wherein a said floating gate (8) and a said control gate (10) are doped polycrystalline silicon layers.
Claim 10
Dependent Claim
18 words
A memory cell array (1) according to Claim 1 wherein a said wordline (13) includes doped polycrystalline silicon.
Claim 11
Dependent Claim
33 words
A memory cell array (1) according to Claim 1 wherein a capacitance associated with a said inter-level dielectric layer (11) is greater than a capacitance associated with a said gate oxide layer (9).
Claim 12
Dependent Claim
18 words
A memory cell array (1) according to Claim 1 wherein said inter-level dielectric layer (11) includes silicon oxide.
Claim 13
Dependent Claim
23 words
A memory cell array according to Claim 1 including sidewall oxide spacers (12) adjacent said control gate (10) and said floating gate (8).
Claim 14
Dependent Claim
28 words
A memory cell array (1) according to Claim 1 wherein at least one of said source-drain regions (SD) adjacent each said channel area (C) has graded impurity concentrations.
Claim 15
Dependent Claim
20 words
A memory cell array (1) according to Claim 1 wherein said gate oxide layer (9) includes a tunnelling region (9a).
Claim 16
Dependent Claim
20 words
A memory cell array (1) according to Claim 1 wherein said underlying channel stop regions (7) are doped with boron.
Claim 17
Dependent Claim
28 words
A memory cell array (1) according to Claim 1 wherein the sides of said floating gates (8) have a grown oxide for the purpose of improved data retention.
References Cited (Backward Citations)
No citation records indexed.
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