US5630094A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated bus bridge and memory controller that enables data streaming to a shared memory of a computer system using snoop ahead transactions
Assignee: Intel Corp
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Filing: 1995-01-20
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Granted: 1997-05-13
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Expires: 2015-01-20
Abstract
Abstract A computer system having an integrated bus bridge and memory controller circuit and method for enabling access to a shared memory with high bandwidth data streaming are disclosed. The integrated bus bridge and memory controller circuit performs a series of snoop ahead transactions over a first bus during access transactions to the shared memory that originate over a second bus and thereby enables high bandwidth data streaming on the second bus. The integrated bus bridge and memory controller circuit includes a peripheral write buffer that buffers write data received over the second bus and that stores a snoop done flag for the write data that indicates whether a corresponding snoop ahead transaction for the write data is complete. The integrated bus bridge and memory controller circuit further includes a peripheral read prefetch buffer that prefetches read data during read transactions over the second bus only after a corresponding snoop ahead transaction for the read data is complete.
Inventors
- 👤 George Hayek
- 👤 Ali S. Oztaskin
- 👤 Brian Langendorf
- 👤 Bruce Young
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 07:00
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0835; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1684; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/405; G06F13/4059
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
176 words
A computer system, comprising: a processor and a cache memory each coupled to a first bus; a main memory; a bus agent coupled to a second bus; and a bus bridge and memory controller circuit coupled to the first bus and the second bus, the bus bridge and memory controller circuit enabling read and write access to the main memory from the first bus and the second bus and also including buffer circuitry for buffering write data, received over the second bus and targeted for the main memory, the bus bridge and memory controller circuit initiating and performing a plurality of snoop ahead transactions to the cache memory over the first bus during memory access transactions originated on the second bus and targeted for the main memory, the bus bridge and memory controller circuit including circuitry for storing, for each of the plurality of snoop ahead transactions, a snoop status indication for indicating if a respective one of the plurality of snoop ahead transactions corresponding to a respective one of the memory access transitions has completed.
Claim 2
Dependent Claim
176 words
A computer system, comprising: a processor and a cache memory each coupled to a first bus; a main memory; a bus agent coupled to a second bus; and a bus bridge and memory controller circuit coupled to the first bus and the second bus, the bus bridge and memory controller circuit enabling read and write access to the main memory from the first bus and the second bus and also including buffer circuitry for buffering write data, received over the second bus and targeted for the main memory, the bus bridge and memory controller circuit initiating and performing a plurality of snoop ahead transactions to the cache memory over the first bus during memory access transactions originated on the second bus and targeted for the main memory, the bus bridge and memory controller circuit including circuitry for storing, for each of the plurality of snoop ahead transactions, a snoop status indication for indicating if a respective one of the plurality of snoop ahead transactions corresponding to a respective one of the memory access transitions has completed.
Claim 3
Dependent Claim
54 words
The computer system of claim 1, wherein the buffer circuitry includes a write buffer, coupled to the main memory, for buffering write data targeted for the main memory, the bus bridge and memory controller circuit including circuitry for memory write data received over the first bus with write data received over the second bus.
Claim 4
Dependent Claim
30 words
The computer system of claim 2, wherein the buffer circuitry includes a peripheral write buffer, coupled to the circuitry for merging, for buffering write data received over the second bus.
Claim 5
Dependent Claim
66 words
The computer system of claim 2, wherein the buffer circuitry includes a peripheral read prefetch buffer, coupled to the second bus, for prefetching read data from the main memory corresponding to the memory access transactions originated on the second bus only after a corresponding one of the plurality of snoop ahead transactions for the read data is complete as indicated by the respective snoop status indication.
Claim 6
Dependent Claim
189 words
A bus bridge and memory controller circuit for use in a computer system having a processor and cache memory, each coupled to a first bus, and a bus agent coupled to a second bus, the bus bridge and memory controller circuit coupled to the first bus and the second bus, the computer system further including a main memory coupled to the bus bridge and memory controller circuit, the bus bridge and memory controller circuit comprising: state machine circuitry for enabling read and write access to the main memory from the first bus and the second bus and for initiating and performing a plurality of snoop ahead transactions to the cache memory over the first bus during memory access transactions originated over the second bus and targeted for the main memory; buffer circuitry for buffering write data received over the second bus and targeted for the main memory; and circuitry for storing, for each of the plurality of snoop ahead transactions, a snoop status indication for indicating if a respective one of the plurality of snoop ahead transactions corresponding to a respective one of the memory access transactions has completed.
Claim 7
Dependent Claim
189 words
A bus bridge and memory controller circuit for use in a computer system having a processor and cache memory, each coupled to a first bus, and a bus agent coupled to a second bus, the bus bridge and memory controller circuit coupled to the first bus and the second bus, the computer system further including a main memory coupled to the bus bridge and memory controller circuit, the bus bridge and memory controller circuit comprising: state machine circuitry for enabling read and write access to the main memory from the first bus and the second bus and for initiating and performing a plurality of snoop ahead transactions to the cache memory over the first bus during memory access transactions originated over the second bus and targeted for the main memory; buffer circuitry for buffering write data received over the second bus and targeted for the main memory; and circuitry for storing, for each of the plurality of snoop ahead transactions, a snoop status indication for indicating if a respective one of the plurality of snoop ahead transactions corresponding to a respective one of the memory access transactions has completed.
Claim 8
Dependent Claim
74 words
The bus bridge and memory controller circuit of claim 5, wherein the buffer circuitry includes a peripheral read prefetch buffer coupled to the second bus, the peripheral read prefetch buffer prefetching read data from the main memory corresponding to the memory access transactions originated on the second bus only after a corresponding one of the plurality of snoop ahead transactions for the read data is complete as indicated by the respective snoop status indication.
Claim 9
Dependent Claim
41 words
The bus bridge and memory controller circuit of claim 5, wherein the state machine circuitry is coupled to the buffer circuitry to control the merging of write data received over the first bus with write data received over the second bus.
Claim 10
Dependent Claim
28 words
The bus bridge and memory controller circuit of claim 7, wherein the buffer circuitry includes a peripheral write buffer for buffering write data received over the second bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-12 | 2000-11-11 | 2001-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-12 | 2004-11-11 | 2005-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-12 | 2008-11-11 | 2009-05-13 | $7700.00 | Window Closed / Lapsed |