Method and apparatus for concurrency of bus operations

Claim 1

A computer system which performs concurrent bus cycle operations, comprising: a host bus; an expansion bus coupled to said host bus; expansion bus memory coupled to said expansion bus, said expansion bus memory storing data; a processor; a cache system coupled to said processor and to said host bus, said cache system including a cache controller and cache memory, wherein said cache controller snoops said host bus when said cache controller does not control said host bus and generates write-back cycles when a snoop hit occurs to a dirty line in said cache memory, wherein said cache controller generates expansion bus read cycles when said processor requests data residing in said expansion bus memory that does not reside in said cache memory; cycle generation means coupled to said cache system and said host bus for generating an expansion bus read cycle after said processor requests data residing in said expansion bus memory that does not reside in said cache memory; a bus master coupled to said host bus which generates cycles onto said host bus which must be snooped by said cache controller; and an expansion bus controller coupled between said host bus and said expansion bus which latches the address of said expansion bus read cycle and obtains said requested data from said expansion bus memory, wherein said expansion bus controller obtains said requested data concurrently with said cache controller snooping said bus master host bus cycle.

Claim 9

A method for performing concurrent operations in a computer system comprising a host bus; a processor coupled to the host bus; a bus master coupled to the host bus; a cache system coupled between the host bus and the processor, the cache system including a cache controller that snoops host bus cycles when said cache controller does not control said host bus and performs write-back cycles when a snoop hit occurs to a dirty line in said cache memory an expansion bus coupled to the host bus; an expansion bus controller coupled between said host bus and said expansion bus; and cache interface logic which generates cache controller cycles onto said host bus, the method comprising: a) the cache controller generating an expansion bus read cycle including an address of requested data; b) the cache interface logic latching said address; c) the cache interface logic presenting said address onto the host bus after step b); d) the expansion bus controller latching said expansion bus read cycle address after step c); e) the bus master performing a host bus cycle that is required to be snooped by the cache controller f) the expansion bus controller performing expansion bus cycles to obtain the requested data after step d); and g) the cache controller snooping said bus master host bus cycle concurrently with step f).

Claim 10

A method for performing concurrent operations in a computer system comprising a host bus; a processor coupled to the host bus; a bus master coupled to the host bus; a cache system coupled between the host bus and the processor, the cache system including a cache controller that snoops host bus cycles when said cache controller does not control said host bus and performs write-back cycles when a snoop hit occurs to a dirty line in said cache memory an expansion bus coupled to the host bus; an expansion bus controller coupled between said host bus and said expansion bus; and cache interface logic which generates cache controller cycles onto said host bus, the method comprising: a) the cache controller generating an expansion bus read cycle including an address of requested data; b) the cache interface logic latching said address; c) the cache interface logic presenting said address onto the host bus after step b); d) the expansion bus controller latching said expansion bus read cycle address after step c); e) the bus master performing a host bus cycle that is required to be snooped by the cache controller f) the expansion bus controller performing expansion bus cycles to obtain the requested data after step d); and g) the cache controller snooping said bus master host bus cycle concurrently with step f).