US5325503A
Expired / Lapsed
US
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Cache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same line
Assignee: Hewlett Packard Development Co LP
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Filing: 1992-02-21
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Granted: 1994-06-28
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Expires: 2012-02-21
Abstract
Abstract A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the same memory location line, then the snoop control logic does not direct the cache to snoop this subsequent access. This eases the snooping burden of the cache and thus increases the efficiency of the processor working out of the cache during this time. When a multilevel cache system is implemented, the snoop control logic directs the cache to snoop certain subsequent accesses to a previously snooped line in order to prevent cache coherency problems from arising. Latency reduction logic which reduces latency problems in the snooping operation of the cache is also included. After every processor read that is transmitted beyond the cache, i.e., cache read misses, the logic gains control of the address inputs of the cache for snooping purposes. The cache no longer needs its address bus for the read cycle and thus the read operation continues unhindered. In addition, the cache is prepared for an upcoming snoop cycle.
Inventors
- 👤 Jeffrey C. Stevens
- 👤 Jens K. Ramsey
- 👤 Randy M. Bonella
- 👤 Philip C. Kelly
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:21
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0835; G06F12/0811; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/161
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
246 words
An apparatus for reducing the snooping requirements of a cache system in a computer system, comprising: a system bus, wherein bus cycles of a first data length execute on said system bus; a processor coupled to said system bus; a cache system coupled between said system bus and said processor, said cache system including a cache memory storing a plurality of lines of data and having a line size comprising a plurality of units of said first data length, wherein said cache system invalidates an entire line on a snoop hit; main memory coupled to said system bus including a plurality of lines storing data corresponding to said cache memory lines, wherein said processor can access said main memory using said system bus; a device coupled to said system bus which can access said main memory using said system bus; means coupled to said cache system and said system bus for directing said cache system to snoop said system bus during a first device main memory access to a first main memory location; and means coupled to said means for directing said cache system to snoop and said system bus for preventing operation of said means for directing said cache system to snoop during a subsequent device main memory access to a main memory location in the same line as said first main memory location, wherein no processor main memory accesses occur between said first device main memory access and said subsequent device main memory access.
Claim 2
Independent Claim
246 words
An apparatus for reducing the snooping requirements of a cache system in a computer system, comprising: a system bus, wherein bus cycles of a first data length execute on said system bus; a processor coupled to said system bus; a cache system coupled between said system bus and said processor, said cache system including a cache memory storing a plurality of lines of data and having a line size comprising a plurality of units of said first data length, wherein said cache system invalidates an entire line on a snoop hit; main memory coupled to said system bus including a plurality of lines storing data corresponding to said cache memory lines, wherein said processor can access said main memory using said system bus; a device coupled to said system bus which can access said main memory using said system bus; means coupled to said cache system and said system bus for directing said cache system to snoop said system bus during a first device main memory access to a first main memory location; and means coupled to said means for directing said cache system to snoop and said system bus for preventing operation of said means for directing said cache system to snoop during a subsequent device main memory access to a main memory location in the same line as said first main memory location, wherein no processor main memory accesses occur between said first device main memory access and said subsequent device main memory access.
Claim 3
Dependent Claim
46 words
The apparatus of claim 1, wherein said means for preventing further includes means coupled to said system bus for determining if said subsequent device main memory access is to the same main memory line as said first main memory location and generating a signal indicative thereof.
Claim 4
Dependent Claim
21 words
The apparatus of claim 2, wherein said subsequent device main memory access occurs immediately after said first device main memory access.
Claim 5
Dependent Claim
25 words
The apparatus of claim 1, wherein said cache system is a write-through cache system and said device main memory accesses are main memory write accesses.
Claim 6
Dependent Claim
27 words
The apparatus of claim 1, wherein said cache system is a write-back cache system, and said cache system invalidates a cache line on a snoop write hit.
Claim 7
Dependent Claim
21 words
The apparatus of claim 5, wherein said device main memory accesses are either main memory read or main memory write accesses.
Claim 8
Dependent Claim
61 words
The apparatus of claim 1, further comprising: a second cache system coupled between said cache system and said system bus, wherein said means for preventing is further coupled to said cache system and does not prevent operation of said means for directing said cache system to snoop after a cache allocation occurs in said cache system from said second cache system.
Claim 9
Dependent Claim
81 words
The apparatus of claim 7, wherein said means for directing said cache system to snoop provides an indication of a cacheable or non-cacheable address to said cache system during cache allocations, said means for directing said cache system to snoop providing a non-cacheable indication to said cache system if said cache system attempts an allocation from said second cache system a period of time after said means for preventing prevents operation of said means for directing said cache system to snoop.
Claim 10
Dependent Claim
27 words
The apparatus of claim 7, wherein said means for directing said cache system to snoop and said means for preventing are located in said second cache system.
Claim 11
Independent Claim
217 words
A method for reducing the snooping requirements of a cache system in a computer system, the computer system comprising: a system bus, wherein bus cycles of a first data length execute on said system bus; a processor coupled to said system bus; a cache system coupled between said processor and said system bus, said cache system including a cache memory storing a plurality of lines of data and having a line size including a plurality of units of said first data length, wherein said cache system invalidates an entire line on a snoop hit; main memory coupled to said system bus including a plurality of lines storing data corresponding to said cache memory lines, wherein said processor can access said main memory using said system bus; and a device coupled to said system bus which can access said main memory using said system bus, the method comprising: directing said cache system to snoop said system bus during a first device main memory access to a first memory location; and preventing execution of said step of directing during a subsequent device main memory access to a memory location in the same line as said first memory location, wherein no processor main memory access occur between said first device main memory access and said subsequent device main memory access.
Claim 12
Independent Claim
217 words
A method for reducing the snooping requirements of a cache system in a computer system, the computer system comprising: a system bus, wherein bus cycles of a first data length execute on said system bus; a processor coupled to said system bus; a cache system coupled between said processor and said system bus, said cache system including a cache memory storing a plurality of lines of data and having a line size including a plurality of units of said first data length, wherein said cache system invalidates an entire line on a snoop hit; main memory coupled to said system bus including a plurality of lines storing data corresponding to said cache memory lines, wherein said processor can access said main memory using said system bus; and a device coupled to said system bus which can access said main memory using said system bus, the method comprising: directing said cache system to snoop said system bus during a first device main memory access to a first memory location; and preventing execution of said step of directing during a subsequent device main memory access to a memory location in the same line as said first memory location, wherein no processor main memory access occur between said first device main memory access and said subsequent device main memory access.
References Cited (Backward Citations)
EP0090575A2
Cited
EP0288649A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-27 | 1997-12-27 | 1998-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-27 | 2001-12-27 | 2002-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-27 | 2005-12-27 | 2006-06-28 | $7700.00 | Window Closed / Lapsed |