Patent US5629643A successfully refreshed from Google Patents.
US5629643A
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US
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Feedback latch and method therefor
Assignee: NXP USA Inc
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Filing: 1996-04-15
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Granted: 1997-05-13
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Expires: 2016-04-15
Abstract
Abstract A latch (40) has a clocked feedback path (46) which performs a static latching function while using less power. The latch includes a feedback device (46) which is selectively decoupled from a feed-forward portion (42, 44) of the latch. In a normal mode of operation when the latch will be clocked often, the feedback device of the latch is not enabled and the latch effectively functions as a dynamic latch. When the latch becomes inactive for an extended period of time, the feedback device is again enabled and the latch is able to store a data value indefinitely.
Inventors
- 👤 Claude Moughanni
- 👤 Jeffrey E. Maguire
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 08:51
CPC Classifications
G; G06; G06F; G06F12/00; H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K3/356113; H03K3/356121; H03K3/01; H03K3/012; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
292 words
A latch comprising: a generation circuit having a first input terminal for receiving a periodic clock signal, a second input terminal for receiving a low power signal, and an output terminal for providing a gated clock signal, said generation circuit providing said periodic clock signal to said output terminal thereof if said low power signal is in a first logic state, said generation circuit providing said gated clock signal at a predetermined logic state if said low power signal is in a second logic state; a first gated inverter having a data input terminal for receiving an input signal of the latch, a control input terminal coupled to said output terminal of said generation circuit, and an output terminal; a second inverter having an input terminal coupled to said output terminal of said first gated inverter, and an output terminal for providing an output signal of the latch; and a third gated inverter having a data input terminal coupled to said output terminal of said second inverter, a control input terminal for receiving said low power signal, and an output terminal coupled to said input terminal of said second inverter, wherein when said low power signal is in said first logic state, said third gated inverter provides an output signal to said output terminal thereof to be a complement of an input signal at said data input terminal thereof, and when said low power signal is in said second logic state, said third gated inverter provides said output signal in a high impedance state; wherein when said low power signal is in said first logic state, said latch functions as a dynamic latch, and when said low power signal is in said second logic state, said latch functions as a static latch.
Claim 2
Dependent Claim
292 words
A latch comprising: a generation circuit having a first input terminal for receiving a periodic clock signal, a second input terminal for receiving a low power signal, and an output terminal for providing a gated clock signal, said generation circuit providing said periodic clock signal to said output terminal thereof if said low power signal is in a first logic state, said generation circuit providing said gated clock signal at a predetermined logic state if said low power signal is in a second logic state; a first gated inverter having a data input terminal for receiving an input signal of the latch, a control input terminal coupled to said output terminal of said generation circuit, and an output terminal; a second inverter having an input terminal coupled to said output terminal of said first gated inverter, and an output terminal for providing an output signal of the latch; and a third gated inverter having a data input terminal coupled to said output terminal of said second inverter, a control input terminal for receiving said low power signal, and an output terminal coupled to said input terminal of said second inverter, wherein when said low power signal is in said first logic state, said third gated inverter provides an output signal to said output terminal thereof to be a complement of an input signal at said data input terminal thereof, and when said low power signal is in said second logic state, said third gated inverter provides said output signal in a high impedance state; wherein when said low power signal is in said first logic state, said latch functions as a dynamic latch, and when said low power signal is in said second logic state, said latch functions as a static latch.
Claim 3
Dependent Claim
173 words
The latch of claim 1 wherein said first gated inverter comprises: a first transistor of a first conductivity type having a first current electrode coupled to a first power supply voltage terminal, a control electrode for receiving a complement of said gated clock signal, and a second current electrode; a second transistor of said first conductivity type having a first current electrode coupled to said second current electrode of said first transistor, a control electrode for receiving said input signal of the latch, and a second current electrode; a third transistor of a second conductivity type having a first current electrode coupled to said second current electrode of said second transistor, a control electrode for receiving said input signal of the latch, and a second current electrode; and a fourth transistor of said second conductivity type having a first current electrode coupled to said second current electrode of said third transistor, a control electrode for receiving said gated clock signal, and a second current electrode coupled to a second power supply voltage terminal.
Claim 4
Dependent Claim
19 words
The latch of claim 2 wherein said first conductivity type is P-channel and said second conductivity type is N-channel.
Claim 5
Dependent Claim
103 words
The latch of claim 2 wherein said generation circuit comprises: a first inverter having an input terminal for receiving said low power signal, and an output terminal for providing said complement of said low power signal; an AND gate having a first input terminal for receiving said periodic dock signal, a second input terminal coupled to said output terminal of said first inverter, and an output terminal for providing said gated clock signal; and a second inverter having an input terminal coupled to said output terminal of said AND gate, and an output terminal for providing said complement of said gated clock signal.
Claim 6
Dependent Claim
175 words
The latch of claim 1 wherein said third gated inverter comprises: a first transistor of a first conductivity type having a first current electrode coupled to a first power supply voltage terminal, a control electrode for receiving a complement of said low power signal, and a second current electrode; a second transistor of said first conductivity type having a first current electrode coupled to said second current electrode of said first transistor, a control electrode coupled to said output terminal of said second inverter, and a second current electrode; a third transistor of a second conductivity type having a first current electrode coupled to said second current electrode of said second transistor, a control electrode coupled to said output terminal of said second inverter, and a second current electrode; and a fourth transistor of said second conductivity type having a first current electrode coupled to said second current electrode of said third transistor, a control electrode for receiving said low power signal, and a second current electrode coupled to a second power supply voltage terminal.
Claim 7
Dependent Claim
19 words
The latch of claim 5 wherein said first conductivity type is P-channel and said second conductivity type is N-channel.
Claim 8
Dependent Claim
74 words
The latch of claim 5 wherein said generation circuit comprises: a first inverter having an input terminal for receiving said low power signal, and an output terminal for providing said complement of said low power signal; and an AND gate having a first input terminal for receiving said periodic clock signal, a second input terminal coupled to said output terminal of said first inverter, and an output terminal for providing said gated clock signal.
Claim 9
Dependent Claim
273 words
In a latch comprising a first gated inverter having a data input terminal for receiving an input signal, a control input terminal, and an output terminal, a second inverter having an input terminal coupled to said output terminal of said first gated inverter, and an output terminal for providing an output signal of the latch, and a third gated inverter having a data input terminal coupled to said output terminal of said second inverter, a control input terminal, and an output terminal coupled to said input terminal of said second inverter, the improvement wherein the latch further comprises: a generation circuit having a first input terminal for receiving a periodic clock signal, a second input terminal for receiving a low power signal, and an output terminal, coupled to said control input terminal of said first gated inverter, for providing a gated clock signal, said generation circuit providing said periodic clock signal to said output terminal thereof if said low power signal is in a first logic state, said generation circuit providing said gated clock signal at a predetermined logic state if said low power signal is in a second logic state; and wherein said third gated inverter further receives said low power signal at said control input terminal thereof, wherein when said low power signal is in said first logic state, said third gated inverter provides an output signal to said output terminal thereof to be a complement of an input signal at said data input terminal thereof, and when said low power signal is in said second logic state, said third gated inverter provides said output signal in a high impedance state.
Claim 10
Dependent Claim
273 words
In a latch comprising a first gated inverter having a data input terminal for receiving an input signal, a control input terminal, and an output terminal, a second inverter having an input terminal coupled to said output terminal of said first gated inverter, and an output terminal for providing an output signal of the latch, and a third gated inverter having a data input terminal coupled to said output terminal of said second inverter, a control input terminal, and an output terminal coupled to said input terminal of said second inverter, the improvement wherein the latch further comprises: a generation circuit having a first input terminal for receiving a periodic clock signal, a second input terminal for receiving a low power signal, and an output terminal, coupled to said control input terminal of said first gated inverter, for providing a gated clock signal, said generation circuit providing said periodic clock signal to said output terminal thereof if said low power signal is in a first logic state, said generation circuit providing said gated clock signal at a predetermined logic state if said low power signal is in a second logic state; and wherein said third gated inverter further receives said low power signal at said control input terminal thereof, wherein when said low power signal is in said first logic state, said third gated inverter provides an output signal to said output terminal thereof to be a complement of an input signal at said data input terminal thereof, and when said low power signal is in said second logic state, said third gated inverter provides said output signal in a high impedance state.
Claim 11
Dependent Claim
167 words
The latch of claim 8 wherein said first gated inverter comprises: a first transistor of a first conductivity type having a first current electrode coupled to a first power supply voltage terminal, a control electrode for receiving a complement of said gated clock signal, and a second current electrode; a second transistor of said first conductivity type having a first current electrode coupled to said second current electrode of said first transistor, a control electrode for receiving said input signal, and a second current electrode; a third transistor of a second conductivity type having a first current electrode coupled to said second current electrode of said second transistor, a control electrode for receiving said input signal, and a second current electrode; and a fourth transistor of said second conductivity type having a first current electrode coupled to said second current electrode of said third transistor, a control electrode for receiving said gated clock signal, and a second current electrode coupled to a second power supply voltage terminal.
Claim 12
Dependent Claim
19 words
The latch of claim 9 wherein said first conductivity type is P-channel and said second conductivity type is N-channel.
Claim 13
Dependent Claim
103 words
The latch of claim 9 wherein said generation circuit comprises: a first inverter having an input terminal for receiving said low power signal, and an output terminal for providing said complement of said low power signal; an AND gate having a first input terminal for receiving said periodic clock signal, a second input terminal coupled to said output terminal of said first inverter, and an output terminal for providing said gated clock signal; and a second inverter having an input terminal coupled to said output terminal of said AND gate, and an output terminal for providing said complement of said gated clock signal.
Claim 14
Dependent Claim
175 words
The latch of claim 8 wherein said third gated inverter comprises: a first transistor of a first conductivity type having a first current electrode coupled to a first power supply voltage terminal, a control electrode for receiving a complement of said low power signal, and a second current electrode; a second transistor of said first conductivity type having a first current electrode coupled to said second current electrode of said first transistor, a control electrode coupled to said output terminal of said second inverter, and a second current electrode; a third transistor of a second conductivity type having a first current electrode coupled to said second current electrode of said second transistor, a control electrode coupled to said output terminal of said second inverter, and a second current electrode; and a fourth transistor of said second conductivity type having a first current electrode coupled to said second current electrode of said third transistor, a control electrode for receiving said low power signal, and a second current electrode coupled to a second power supply voltage terminal.
Claim 15
Dependent Claim
19 words
The latch of claim 12 wherein said first conductivity type is P-channel and said second conductivity type is N-channel.
Claim 16
Dependent Claim
74 words
The latch of claim 12 wherein said generation circuit comprises: a first inverter having an input terminal for receiving said low power signal, and an output terminal for providing said complement of said low power signal; and an AND gate having a first input terminal for receiving said periodic clock signal, a second input terminal coupled to said output terminal of said first inverter, and an output terminal for providing said gated clock signal.
Claim 17
Independent Claim
184 words
A method for operating a latch, the latch comprising a first gated inverter having an input terminal for receiving an input signal of the latch and an output terminal, a second inverter having an input terminal coupled to the output terminal of the first gated inverter, and an output terminal for providing an output of the latch, and a third gated inverter having a data input terminal coupled to the output terminal of the second inverter, and an output terminal coupled to the input terminal of the second inverter, comprising the steps of: clocking the first gated inverter with a periodic clock input signal in a normal operation mode; disabling the third gated inverter in said normal operation mode; disabling the first gated inverter in a low power mode; and enabling the third gated inverter in response to entering said low power mode, wherein the latch functions as a dynamic latch using the first gated inverter and the second inverter in the normal operation mode, and as a static latch using the second inverter and the third gated inverter in the low power mode.
Claim 18
Independent Claim
184 words
A method for operating a latch, the latch comprising a first gated inverter having an input terminal for receiving an input signal of the latch and an output terminal, a second inverter having an input terminal coupled to the output terminal of the first gated inverter, and an output terminal for providing an output of the latch, and a third gated inverter having a data input terminal coupled to the output terminal of the second inverter, and an output terminal coupled to the input terminal of the second inverter, comprising the steps of: clocking the first gated inverter with a periodic clock input signal in a normal operation mode; disabling the third gated inverter in said normal operation mode; disabling the first gated inverter in a low power mode; and enabling the third gated inverter in response to entering said low power mode, wherein the latch functions as a dynamic latch using the first gated inverter and the second inverter in the normal operation mode, and as a static latch using the second inverter and the third gated inverter in the low power mode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-12 | 2000-11-11 | 2001-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-12 | 2004-11-11 | 2005-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-12 | 2008-11-11 | 2009-05-13 | $7700.00 | Window Closed / Lapsed |