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US5627787A
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Periphery stress test for synchronous RAMs
Assignee: STMicroelectronics lnc USA
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Filing: 1995-01-03
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Granted: 1997-05-06
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Expires: 2015-01-03
Abstract
Abstract According to the method of the present invention, stress testing of decoders and other periphery circuits of synchronous RAMs is performed within a reasonable period of time and without an increase in the complexity of stress testing or fabrication of synchronous RAMs. In order to stress test decoders and periphery circuits of a synchronous RAM to obtain maximum fault coverage of possible latent defects, a periphery stress mode is defined through appropriate manipulation of the Power-On Reset signal of the device such that all nodes of a memory array of the synchronous RAM are pulled in the opposite logic state from that required for a memory cell stress mode. In the periphery stress mode, the Power-On Reset signal is allowed to pulse upon power-up of the synchronous RAM device such that latches and flip flops of the device are forced in a logic state that disables all rows and columns of the memory array of the device. Additionally, all D.C. (direct current) paths of the synchronous RAM are disabled so that a high power supply voltage may be applied during the periphery stress mode without fear of transistor "snap back voltage". Thus, once all D.C. paths of the synchronous RAM are disabled, a Vcc voltage level as high as ten volts may be applied during the periphery stress mode without experiencing transistor impact ionization due to high substrate current, known as BVDII or "snap back voltage".
Inventors
- 👤 David C. McClure
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:04
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/02; G11C29/024; G11C29/04; G11C29/50; G11C8/00; G11C8/12; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41
Claims Analysis
Total Claims: 47
Claim 1
Independent Claim
83 words
A method for stress testing decoders and periphery circuits of a synchronous RAM (Random Access Memory) comprising the steps of: entering a periphery stress mode by forcing a control signal of a synchronous RAM to a first logic level; and applying a stress voltage to the synchronous RAM in order to stress test a plurality of decoders of the synchronous RAM, wherein entry into and exit from the periphery stress mode is accomplished through a wafer level test pin of the synchronous RAM.
Claim 2
Independent Claim
83 words
A method for stress testing decoders and periphery circuits of a synchronous RAM (Random Access Memory) comprising the steps of: entering a periphery stress mode by forcing a control signal of a synchronous RAM to a first logic level; and applying a stress voltage to the synchronous RAM in order to stress test a plurality of decoders of the synchronous RAM, wherein entry into and exit from the periphery stress mode is accomplished through a wafer level test pin of the synchronous RAM.
Claim 3
Independent Claim
86 words
A method for stress testing decoders and periphery circuits of a synchronous RAM (Random Access Memory) comprising the steps of: entering a periphery stress mode by forcing a control signal of a synchronous RAM to a first logic level; and applying a stress voltage to the synchronous RAM in order to stress test a plurality of decoders of the synchronous RAM, wherein entry into and exit from the periphery stress mode is accomplished by applying a super voltage to a package pin of the synchronous RAM.
Claim 4
Independent Claim
86 words
A method for stress testing decoders and periphery circuits of a synchronous RAM (Random Access Memory) comprising the steps of: entering a periphery stress mode by forcing a control signal of a synchronous RAM to a first logic level; and applying a stress voltage to the synchronous RAM in order to stress test a plurality of decoders of the synchronous RAM, wherein entry into and exit from the periphery stress mode is accomplished by applying a super voltage to a package pin of the synchronous RAM.
Claim 5
Independent Claim
78 words
A method for stress testing decoders and periphery circuits of a synchronous RAM (Random Access Memory) comprising the steps of: entering a periphery stress mode by forcing a control signal of a synchronous RAM to a first logic level; and applying a stress voltage to the synchronous RAM in order to stress test a plurality of decoders of the synchronous RAM, wherein the control signal allows pulsing of a power-on reset signal while in the periphery stress mode.
Claim 6
Independent Claim
78 words
A method for stress testing decoders and periphery circuits of a synchronous RAM (Random Access Memory) comprising the steps of: entering a periphery stress mode by forcing a control signal of a synchronous RAM to a first logic level; and applying a stress voltage to the synchronous RAM in order to stress test a plurality of decoders of the synchronous RAM, wherein the control signal allows pulsing of a power-on reset signal while in the periphery stress mode.
Claim 7
Dependent Claim
16 words
The method of claim 3, wherein each decoder of the plurality of decoders contains a latch.
Claim 8
Dependent Claim
33 words
The method of claim 4, wherein the latch which couples to the decoder, is forced to a second logic level which results in a plurality of elements controlled by the decoder being deselected.
Claim 9
Dependent Claim
22 words
The method of claim 5, wherein the decoder is a row decoder and the plurality of elements are a plurality of rows.
Claim 10
Dependent Claim
22 words
The method of claim 5, wherein the decoder is a column decoder and the plurality of elements are a plurality of columns.
Claim 11
Dependent Claim
21 words
The method of claim 5, wherein the latch is forced to the second logic level while in the periphery stress mode.
Claim 12
Dependent Claim
23 words
The method of claim 5, wherein the latch is forced to the second logic level upon a power-up condition of the synchronous RAM.
Claim 13
Dependent Claim
32 words
The method of claim 3, wherein upon power-up of the Synchronous RAM, the power-on reset signal is allowed to pulse such that the plurality of decoders are each in a deselecting state.
Claim 14
Dependent Claim
36 words
The method of claim 10, wherein a plurality of rows and a plurality of columns of the synchronous RAM are deselected when, upon power-up of the synchronous RAM, the power-on reset signal is allowed to pulse.
Claim 15
Independent Claim
89 words
A method for stress testing decoders and periphery circuits of a synchronous RAM (Random Access Memory) comprising the steps of: entering a periphery stress mode by forcing a control signal of a synchronous RAM to a first logic level; and applying a stress voltage to the synchronous RAM in order to stress test a plurality of decoders of the synchronous RAM wherein forcing the control signal of the synchronous RAM to the first logic level causes each decoder of the plurality of decoders to be in a deselecting state.
Claim 16
Independent Claim
89 words
A method for stress testing decoders and periphery circuits of a synchronous RAM (Random Access Memory) comprising the steps of: entering a periphery stress mode by forcing a control signal of a synchronous RAM to a first logic level; and applying a stress voltage to the synchronous RAM in order to stress test a plurality of decoders of the synchronous RAM wherein forcing the control signal of the synchronous RAM to the first logic level causes each decoder of the plurality of decoders to be in a deselecting state.
Claim 17
Independent Claim
72 words
A method for stress testing decoders and periphery circuits of a synchronous RAM (Random Access Memory), comprising the steps of: disabling a plurality of direct current paths of a synchronous RAM; entering a periphery stress mode by forcing a control signal of a synchronous RAM to a first logic level; and applying a stress voltage to the synchronous RAM in order to stress test a plurality of decoders of the synchronous RAM.
Claim 18
Independent Claim
72 words
A method for stress testing decoders and periphery circuits of a synchronous RAM (Random Access Memory), comprising the steps of: disabling a plurality of direct current paths of a synchronous RAM; entering a periphery stress mode by forcing a control signal of a synchronous RAM to a first logic level; and applying a stress voltage to the synchronous RAM in order to stress test a plurality of decoders of the synchronous RAM.
Claim 19
Independent Claim
94 words
A method for stress testing decoders and periphery circuits of a synchronous RAM (Random Access Memory), comprising the steps of: disabling a plurality of direct current paths of a synchronous RAM; entering a periphery stress mode by forcing a control signal of the synchronous RAM to a first logic level, wherein entry into and exit from the periphery stress mode is accomplished through a wafer level test pin of the synchronous RAM; and applying a stress voltage to the synchronous RAM in order to stress test a plurality of decoders of the synchronous RAM.
Claim 20
Independent Claim
94 words
A method for stress testing decoders and periphery circuits of a synchronous RAM (Random Access Memory), comprising the steps of: disabling a plurality of direct current paths of a synchronous RAM; entering a periphery stress mode by forcing a control signal of the synchronous RAM to a first logic level, wherein entry into and exit from the periphery stress mode is accomplished through a wafer level test pin of the synchronous RAM; and applying a stress voltage to the synchronous RAM in order to stress test a plurality of decoders of the synchronous RAM.
Claim 21
Dependent Claim
30 words
The method of claim 13, wherein entry into and exit from the periphery stress mode is accomplished by applying a super voltage to a package pin of the synchronous RAM.
Claim 22
Dependent Claim
27 words
The method of claim 13, wherein disabling the plurality of direct current paths of the synchronous RAM disables a slew rate control circuit of the synchronous RAM.
Claim 23
Dependent Claim
27 words
The method of claim 13, wherein disabling the plurality of direct current paths of the synchronous RAM disables an output voltage bias circuit of the synchronous RAM.
Claim 24
Independent Claim
89 words
A method for stress testing decoders and periphery circuits of a synchronous RAM (Random Access Memory), comprising the steps of: disabling a plurality of direct current paths of a synchronous RAM; entering a periphery stress mode by forcing a control signal of the synchronous RAM to a first logic level; and applying a stress voltage to the synchronous RAM in order to stress test a plurality of decoders of the synchronous RAM wherein the control signal allows pulsing of a power-on reset signal while in the periphery stress mode.
Claim 25
Independent Claim
89 words
A method for stress testing decoders and periphery circuits of a synchronous RAM (Random Access Memory), comprising the steps of: disabling a plurality of direct current paths of a synchronous RAM; entering a periphery stress mode by forcing a control signal of the synchronous RAM to a first logic level; and applying a stress voltage to the synchronous RAM in order to stress test a plurality of decoders of the synchronous RAM wherein the control signal allows pulsing of a power-on reset signal while in the periphery stress mode.
Claim 26
Dependent Claim
16 words
The method of claim 18, wherein each decoder of the plurality of decoders contains a latch.
Claim 27
Dependent Claim
33 words
The method of claim 19, wherein the latch, which couples to the decoder, is forced to a second logic level which results in a plurality of elements controlled by the decoder being deselected.
Claim 28
Dependent Claim
22 words
The method of claim 20, wherein the decoder is a row decoder and the plurality of elements are a plurality of rows.
Claim 29
Dependent Claim
21 words
The method of claim 20, wherein the decoder is column decoder and the plurality of elements are a plurality of columns.
Claim 30
Dependent Claim
21 words
The method of claim 20, wherein the latch is forced to the second logic level while in the periphery stress mode.
Claim 31
Dependent Claim
23 words
The method of claim 20, wherein the latch is forced to the second logic level upon a power-up condition of the synchronous RAM.
Claim 32
Dependent Claim
32 words
The method of claim 18, wherein upon power-up of the synchronous RAM, the power-on reset signal is allowed to pulse such that the plurality of decoders are each in a deselecting state.
Claim 33
Dependent Claim
36 words
The method of claim 25, wherein a plurality of rows and a plurality of columns of the synchronous RAM are deselected when, upon power-up of the synchronous RAM, the power-on reset signal is allowed to pulse.
Claim 34
Dependent Claim
33 words
The method of claim 13, wherein forcing the control signal of the synchronous RAM to the first logic level causes each decoder of the plurality of decoders to be in a deselecting state.
Claim 35
Independent Claim
104 words
A method for stress testing decoders and periphery circuits of a synchronous RAM (Random Access Memory), comprising the steps of: disabling a plurality of direct current paths of a synchronous RAM, wherein disabling the plurality of direct current paths disables the direct current paths of the synchronous RAM such that a plurality of transistors of the synchronous RAM are not operating in saturation; entering a periphery stress mode by forcing a control signal of the synchronous RAM to a first logic level; and applying a stress voltage to the synchronous RAM in order to stress test a plurality of decoders of the synchronous RAM.
Claim 36
Independent Claim
104 words
A method for stress testing decoders and periphery circuits of a synchronous RAM (Random Access Memory), comprising the steps of: disabling a plurality of direct current paths of a synchronous RAM, wherein disabling the plurality of direct current paths disables the direct current paths of the synchronous RAM such that a plurality of transistors of the synchronous RAM are not operating in saturation; entering a periphery stress mode by forcing a control signal of the synchronous RAM to a first logic level; and applying a stress voltage to the synchronous RAM in order to stress test a plurality of decoders of the synchronous RAM.
Claim 37
Independent Claim
102 words
A method for stress testing decoders and periphery circuits of a synchronous RAM (Random Access Memory), comprising the steps of: disabling a plurality of direct current paths of a synchronous RAM, wherein disabling the plurality of direct current paths allows a large value of the stress voltage to be applied to the synchronous RAM without causing a "snap back voltage" phenomenon; entering a periphery stress mode by forcing a control signal of the synchronous RAM to a first logic level; and applying a stress voltage to the synchronous RAM in order to stress test a plurality of decoders of the synchronous RAM.
Claim 38
Independent Claim
102 words
A method for stress testing decoders and periphery circuits of a synchronous RAM (Random Access Memory), comprising the steps of: disabling a plurality of direct current paths of a synchronous RAM, wherein disabling the plurality of direct current paths allows a large value of the stress voltage to be applied to the synchronous RAM without causing a "snap back voltage" phenomenon; entering a periphery stress mode by forcing a control signal of the synchronous RAM to a first logic level; and applying a stress voltage to the synchronous RAM in order to stress test a plurality of decoders of the synchronous RAM.
Claim 39
Dependent Claim
22 words
The method of claim 29, wherein the stress voltage applied to the synchronous RAM is between approximately 7 volts and 10 volts.
Claim 40
Dependent Claim
18 words
The method of claim 13, wherein the plurality of decoders are a plurality of global word line decoders.
Claim 41
Dependent Claim
16 words
The method of claim 13, wherein the plurality of decoders are a plurality of column decoders.
Claim 42
Dependent Claim
16 words
The method of claim 13, wherein the plurality of decoders are a plurality of row decoders.
Claim 43
Dependent Claim
16 words
The method of claim 13, wherein the plurality of decoders are a plurality of write decoders.
Claim 44
Dependent Claim
16 words
The method of claim 13, wherein the plurality of decoders are a plurality of pre-decoding circuits.
Claim 45
Dependent Claim
16 words
The method of claim 13, wherein the plurality of decoders are a plurality of post-decoding circuits.
Claim 46
Dependent Claim
13 words
The method of claim 13, wherein the synchronous RAM is a Burst RAM.
Claim 47
Dependent Claim
41 words
The method of claim 13, wherein the step of entering the periphery stress mode is performed after the step of applying the stress voltage to the synchronous RAM in order to stress test a plurality of decoders of the synchronous RAM.
References Cited (Backward Citations)
US5287312A
Cited
US5357193A
Cited
US5424988A
Cited
US5341336A
Cited
US5379260A
Cited
US5455799A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-05 | 2000-11-04 | 2001-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-05 | 2004-11-04 | 2005-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-05 | 2008-11-04 | 2009-05-06 | $7700.00 | Window Closed / Lapsed |