Semiconductor memory having a voltage stress applying circuit

Claim 1

A semiconductor memory operable in a normal operation and a voltage stress test operation comprising: a plurality of dynamic memory cells arranged in rows and columns; bit lines, each bit line being connected to dynamic memory cells of a corresponding column; word lines, each word line being connected to dynamic memory cells of a corresponding row; a bit line precharge power source line for supplying a precharge voltage to said bit lines; a bit line precharge circuit connected between said bit line precharge power source line and said bit lines; a bit line precharge signal generation circuit connected to said bit line precharge circuit and controlled so as to be in one of (i) an active state in which a precharge control signal is generated for setting said bit line precharge circuit in an ON state when a control signal is input from an external portion, and (ii) an inactive state in which the precharge control signal is not generated; a first pad to which a stress voltage is applied from the external portion during the voltage stress test operation; a first switching circuit connected between said first pad and a first predetermined number of word lines, the first predetermined number of word lines being larger than a second predetermined number of word lines selected during the normal operation in accordance with a word line selecting signal, said first switching circuit transmitting the stress voltage to the first predetermined number of word lines at a time when the stress voltage is applied to said first pad; and a control circuit controlled by one of the stress voltage applied to said first pad and a stress test control voltage supplied to said first switching circuit, said control circuit controlling said bit line precharge signal generation circuit to be active in the voltage stress testing operation.