Patent US5627624A successfully refreshed from Google Patents.
US5627624A
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Integrated circuit test reticle and alignment mark optimization method
Assignee: LSI Corp
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Filing: 1994-10-31
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Granted: 1997-05-06
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Expires: 2014-10-31
Abstract
Abstract A test reticle and alignment mark optimization method is provided for determining the optimal alignment mark size for the efficient and accurate alignment of process layers during integrated circuit manufacture. The test reticle includes a number of orthogonally arranged alignment marks of various types and sizes and one or more registration structures. The method involves the steps of determining an initial expected range of alignment mark sizes on the test reticle which are suitable for a particular application; applying the test reticle patter to test wafers; further processing the test wafers; measuring the alignment signals produced by scanning the alignment marks in the initial expected range; quantifying the alignment signal quality; and fitting the quantified alignment signal quality to a statistical model to determine a range of optimal alignment signal dimensions.
Inventors
- 👤 Randy Yim
- 👤 Christopher Neville
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 19:49
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/70; G03F7/70483; G03F7/70605; G03F7/70616; G03F7/70633; G03F1/00; G03F1/38; G03F1/42; G03F1/44; G03F9/00; G03F9/70
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
114 words
A method of fabricating a semiconductor integrated circuit including a plurality of overlying process layers, comprising the steps of: (a) providing a test reticle having a pattern including a plurality of groups of different types of alignment marks, with each group including a plurality of different sizes of said alignment marks respectively; (b) applying the test reticle to form said pattern on a test wafer; (c) sensing a selected group of said alignment marks of said pattern on the test wafer to determine an optimal size for said alignment marks thereof; and (d) fabricating said integrated circuit using alignment marks of said selected group and said optimal size to align said overlying process layers.
Claim 2
Independent Claim
114 words
A method of fabricating a semiconductor integrated circuit including a plurality of overlying process layers, comprising the steps of: (a) providing a test reticle having a pattern including a plurality of groups of different types of alignment marks, with each group including a plurality of different sizes of said alignment marks respectively; (b) applying the test reticle to form said pattern on a test wafer; (c) sensing a selected group of said alignment marks of said pattern on the test wafer to determine an optimal size for said alignment marks thereof; and (d) fabricating said integrated circuit using alignment marks of said selected group and said optimal size to align said overlying process layers.
Claim 3
Dependent Claim
20 words
A method as in claim 1, in which step (a) comprises providing said pattern as further including a registration structure.
Claim 4
Dependent Claim
22 words
A method as in claim 2, in which step (c) comprises performing a registration on the test wafer using said registration structure.
Claim 5
Dependent Claim
47 words
A method as in claim 1, in which step (c) comprises the substeps of: (e) optoelectronically scanning said pattern on the test wafer to produce electrical signals corresponding to said alignment marks; and (f) analyzing said electrical signals using a predetermined criteria to determine said optimal size.
Claim 6
Dependent Claim
27 words
A method as in claim 1, further comprising the step, performed between steps (b) and (c), of: (e) subjecting the test wafer to an additional processing step.
Claim 7
Dependent Claim
26 words
A method as in claim 1, in which step (a) comprises providing the test reticle such that said alignment marks are formed in an orthogonal pattern.
Claim 8
Dependent Claim
26 words
A method as in claim 1, in which step (a) comprises providing the test reticle such that said alignment marks are formed in a non-orthogonal pattern.
Claim 9
Dependent Claim
114 words
A semiconductor integrated circuit including a plurality of overlying process layers, fabricated by a method comprising the steps of: (a) providing a test reticle having a pattern including a plurality of groups of different types of alignment marks, with each group including a plurality of different sizes of said alignment marks respectively; (b) applying the test reticle to form said pattern on a test wafer; (c) sensing a selected group of said alignment marks of said pattern on the test wafer to determine an optimal size for said alignment marks thereof; and (d) fabricating said integrated circuit using alignment marks of said selected group and said optimal size to align said overlying process layers.
Claim 10
Dependent Claim
114 words
A semiconductor integrated circuit including a plurality of overlying process layers, fabricated by a method comprising the steps of: (a) providing a test reticle having a pattern including a plurality of groups of different types of alignment marks, with each group including a plurality of different sizes of said alignment marks respectively; (b) applying the test reticle to form said pattern on a test wafer; (c) sensing a selected group of said alignment marks of said pattern on the test wafer to determine an optimal size for said alignment marks thereof; and (d) fabricating said integrated circuit using alignment marks of said selected group and said optimal size to align said overlying process layers.
Claim 11
Dependent Claim
20 words
A method as in claim 8, in which step (a) comprises providing said pattern as further including a registration structure.
Claim 12
Dependent Claim
22 words
A method as in claim 9, in which step (c) comprises performing a registration on the test wafer using said registration structure.
Claim 13
Dependent Claim
47 words
A method as in claim 8, in which step (c) comprises the substeps of: (e) optoelectronically scanning said pattern on the test wafer to produce electrical signals corresponding to said alignment marks; and (f) analyzing said electrical signals using a predetermined criteria to determine said optimal size.
Claim 14
Dependent Claim
27 words
A method as in claim 8, further comprising the step, performed between steps (b) and (c), of: (e) subjecting the test wafer to an additional processing step.
Claim 15
Dependent Claim
26 words
A method as in claim 8, in which step (a) comprises providing the test reticle such that said alignment marks are formed in an orthogonal pattern.
Claim 16
Dependent Claim
26 words
A method as in claim 8, in which step (a) comprises providing the test reticle such that said alignment marks are formed in a non-orthogonal pattern.
Claim 17
Dependent Claim
100 words
An archive wafer fabricated by a method comprising the steps of: (a) providing a test reticle having a pattern including a plurality of groups of different types of alignment marks, with each group including a plurality of different sizes of said alignment marks respectively; (b) applying the test reticle to form said pattern on a test wafer; (c) sensing a selected group of said alignment marks of said pattern on the test wafer to determine an optimal size for said alignment marks thereof; and (d) forming alignment marks of said selected group and said optimal size on the archive wafer.
Claim 18
Dependent Claim
100 words
An archive wafer fabricated by a method comprising the steps of: (a) providing a test reticle having a pattern including a plurality of groups of different types of alignment marks, with each group including a plurality of different sizes of said alignment marks respectively; (b) applying the test reticle to form said pattern on a test wafer; (c) sensing a selected group of said alignment marks of said pattern on the test wafer to determine an optimal size for said alignment marks thereof; and (d) forming alignment marks of said selected group and said optimal size on the archive wafer.
Claim 19
Dependent Claim
21 words
An archive wafer as in claim 15, in which step (a) comprises providing said pattern as further including a registration structure.
Claim 20
Dependent Claim
23 words
An archive wafer as in claim 16, in which step (c) comprises performing a registration on the test wafer using said registration structure.
Claim 21
Dependent Claim
48 words
An archive wafer as in claim 15, in which step (c) comprises the substeps of: (e) optoelectronically scanning said pattern on the test wafer to produce electrical signals corresponding to said alignment marks; and (f) analyzing said electrical signals using a predetermined criteria to determine said optimal size.
Claim 22
Dependent Claim
28 words
An archive wafer as in claim 15, further comprising the step, performed between steps (b) and (c), of: (e) subjecting the test wafer to an additional processing step.
Claim 23
Dependent Claim
27 words
An archive wafer as in claim 15, in which step (a) comprises providing the test reticle such that said alignment marks are formed in an orthogonal pattern.
Claim 24
Dependent Claim
27 words
An archive wafer as in claim 15, in which step (a) comprises providing the test reticle such that said alignment marks are formed in a non-orthogonal pattern.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2000-05-05 | 2000-11-04 | 2001-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-05 | 2004-11-04 | 2005-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-05 | 2008-11-04 | 2009-05-06 | $7700.00 | Window Closed / Lapsed |