Voltage regulator bypass circuit

Claim 1

A regulator circuit for a multi-voltage compatible integrated circuit chip comprising: a first power rail connected to an externally supplied voltage Vcc; a second power rail internal to said integrated circuit chip, a regulated voltage Vdd being applied to said second power rail where Vdd is less than Vcc; a third power rail internal to said integrated circuit chip, said third power rail being a ground voltage Vss; a voltage regulator connected between said first and second power rails for lowering the voltage Vcc on said first power rail to a required voltage Vdd on said second power rail; and an electrically triggered bypass network connected between said first power rail and said second power rail, said bypass network detecting an onset of an over voltage condition on said first power rail and bypassing said voltage regulator by providing a shunt current path from said first power rail to said second power rail, said electrically triggerable bypass network comprising a rise time network connected to said first power rail for generating a first delayed output voltage level; a level shift network responsive to said first delayed output voltage level for generating a first logic level; a logic gate connected to receive as inputs said first logic level and the second power rail, said logic gate generating a control output; and a bypass network connected between said first and second power rails and controlled by said control output for providing a shunt path from said first power rail to said second power rail.