US5287241A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Shunt circuit for electrostatic discharge protection
Assignee: Cirrus Logic Inc
•
Filing: 1992-02-04
•
Granted: 1994-02-15
•
Expires: 2012-02-04
Abstract
Abstract A circuit is added to a complementary metal-oxide silicon (CMOS) integrated circuit (IC) to provide an intentional, non-reverse-biased VDD-to-VSS shunt path for transient currents such as electrostatic discharges (ESD). This circuit protects the IC from ESD damage by turning on before any other path, thus directing the ESD transient current away from easily damaged structures. Specifically, the ESD transient current is steered from the VDD rail to the VSS rail through the on conduction of a P-channel transistor whose source and drain are connected to VDD and VSS respectively. The voltage on the gate of this transistor follows the VDD supply rail because it is driven by a delay network formed by a second transistor and a capacitor. This VDD-tracking delay network turns the VDD-to-VSS transistor on during a transient and off during normal operation of the IC.
Inventors
- 👤 Deepraj S. Puar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:45
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
119 words
A transient protection circuit for an integrated circuit, at least part of which is a CMOS circuit having a VDD power supply rail and a VSS power supply rail supplying power to said CMOS circuit, comprising: a first P-channel MOS transistor having a source coupled to said VDD supply rail, a drain coupled to said VSS supply rail, and a gate; a second MOS transistor having a drain coupled to the gate of the first transistor, a source coupled to said VDD supply rail, and a gate coupled to said VSS supply rail; and, a capacitor having a first capacitor connection to said gate of said first transistor and a second capacitor connection coupled to said VSS supply rail.
Claim 2
Dependent Claim
119 words
A transient protection circuit for an integrated circuit, at least part of which is a CMOS circuit having a VDD power supply rail and a VSS power supply rail supplying power to said CMOS circuit, comprising: a first P-channel MOS transistor having a source coupled to said VDD supply rail, a drain coupled to said VSS supply rail, and a gate; a second MOS transistor having a drain coupled to the gate of the first transistor, a source coupled to said VDD supply rail, and a gate coupled to said VSS supply rail; and, a capacitor having a first capacitor connection to said gate of said first transistor and a second capacitor connection coupled to said VSS supply rail.
Claim 3
Dependent Claim
16 words
A circuit as in claim 1, wherein said second MOS transistor is a P-channel MOS transistor.
Claim 4
Dependent Claim
43 words
A circuit as in any one of claims 1 or 2 wherein said capacitor is implemented as a MOS transistor having a gate forming one of said capacitor connections and having a source and drain coupled together forming the other said capacitor connection.
Claim 5
Dependent Claim
37 words
A circuit as in claim 3 wherein said capacitor is implemented as a P-channel MOS transistor having a gate forming said second capacitor connection and having a source and drain coupled together forming said first capacitor connection.
Claim 6
Dependent Claim
37 words
A circuit as in claim 3 wherein said capacitor is implemented as an N-channel MOS transistor having a gate forming said first capacitor connection and having a source and drain coupled together forming said second capacitor connection.
Claim 7
Dependent Claim
22 words
The circuit of claim 1 wherein the threshold of the P-channel transistor is less than the operating voltage of the integrated circuit.
Claim 8
Dependent Claim
37 words
A circuit as in claim 3 wherein said capacitor is implemented as an N-channel MOS transistor having a gate forming said second capacitor connection and having a source and drain coupled together forming said first capacitor connection.
Claim 9
Dependent Claim
77 words
A transient protection circuit for an integrated circuit, at least part of which is a CMOS circuit having a VDD power supply rail and a VSS power supply rail supplying power to said CMOS circuit, comprising: a P-channel MOS transistor having a source coupled to said VDD supply rail, a drain coupled to said VSS supply rail, and a gate, and a VDD-tracking delay circuit having an output terminal coupled to the gate terminal of the transistor.
Claim 10
Dependent Claim
77 words
A transient protection circuit for an integrated circuit, at least part of which is a CMOS circuit having a VDD power supply rail and a VSS power supply rail supplying power to said CMOS circuit, comprising: a P-channel MOS transistor having a source coupled to said VDD supply rail, a drain coupled to said VSS supply rail, and a gate, and a VDD-tracking delay circuit having an output terminal coupled to the gate terminal of the transistor.
Claim 11
Dependent Claim
15 words
A circuit as in claim 8, wherein said VDD-tracking delay circuit comprises an RC network.
Claim 12
Dependent Claim
44 words
A circuit as in claim 9, wherein said RC network comprises a resistance coupled between said gate of said P-channel MOS transistor and said VDD supply rail and a capacitance coupled between said gate of said P-channel MOS transistor and said VSS supply rail.
Claim 13
Dependent Claim
42 words
A circuit as in claim 10, wherein said resistance comprises a MOS transistor biased on and said capacitance comprises a MOS transistor having a gate forming one capacitor connection and having a source and drain coupled together forming the other capacitor connection.
Claim 14
Dependent Claim
16 words
A circuit as in claim 11, wherein said capacitor is implemented as an P-channel MOS transistor.
Claim 15
Dependent Claim
16 words
A circuit as in claim 11, wherein said capacitor is implemented as an N-channel MOS transistor.
Claim 16
Dependent Claim
124 words
A transient protection circuit for an integrated circuit, at least part of which is a CMOS circuit, and having a VDD and a VSS power supply rail supplying power to said CMOS circuit, comprising: a P-channel MOS transistor having a source coupled to said VDD supply rail, a drain coupled to said VSS supply rail, and a gate; and, circuit means coupled to said gate of said P-channel MOS transistor for imposing at least a substantial part of a very short term transient VDD to VSS voltage change, caused by an electrostatic discharge, onto said P-channel MOS transistor as a source to gate voltage, thereby turning on said P-channel MOS transistor to limit the DD to VSS voltage change caused by the electrostatic discharge.
Claim 17
Dependent Claim
124 words
A transient protection circuit for an integrated circuit, at least part of which is a CMOS circuit, and having a VDD and a VSS power supply rail supplying power to said CMOS circuit, comprising: a P-channel MOS transistor having a source coupled to said VDD supply rail, a drain coupled to said VSS supply rail, and a gate; and, circuit means coupled to said gate of said P-channel MOS transistor for imposing at least a substantial part of a very short term transient VDD to VSS voltage change, caused by an electrostatic discharge, onto said P-channel MOS transistor as a source to gate voltage, thereby turning on said P-channel MOS transistor to limit the DD to VSS voltage change caused by the electrostatic discharge.
Claim 18
Dependent Claim
101 words
The transient protection circuit of claim 14 wherein said means for imposing at least a substantial part of a very short term transient VDD to VSS voltage change, caused by an electrostatic discharge, onto said P-channel MOS transistor as a source to gate voltage is also a means for not imposing a substantial part of the VDD to VSS voltage change, caused by power supply voltage changes, onto said P-channel MOS transistor as a source to gate voltage, thereby not turning on said P-channel MOS transistor to limit the VDD to VSS voltage change caused by the power supply voltage changes.
Claim 19
Dependent Claim
22 words
The circuit of claim 14 wherein the threshold of the P-channel transistor is less than the operating voltage of the integrated circuit.
Claim 20
Dependent Claim
22 words
The circuit of claim 18 wherein the threshold of the P-channel transistor is less than the operating voltage of the integrated circuit.
References Cited (Backward Citations)
US4595941A
Cited
US5189588A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-14 | 1997-08-16 | 1998-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-14 | 2001-08-16 | 2002-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-14 | 2005-08-16 | 2006-02-15 | $7700.00 | Window Closed / Lapsed |