ECL gate array semiconductor device with protective elements

Claim 1

A semiconductor device comprising: a semiconductor chip; a high potential level power supply line arranged on said peripheral portion of said chip; an internal gate region having a plurality of internal gates arranged on a central portion of the chip, said internal gate comprising an ECL gate having a pair of transistors with commonly connected emitters and collectors operatively connected to said high potential level power supply line through a resistor; a plurality of emitter-follower-type output transistors arranged on a peripheral region of said chip and on an outer region of said internal gate region, said output transistors having a collector operatively connected to said high potential level power supply line, a base for receiving signals from said internal gates and an emitter for outputting signals to an external portion of said semiconductor device, said output transistors being NPN type; a plurality of input/output pads arranged on said peripheral region of said chip and on an outer region of said emitter-follower-type output transistors, said input/output pads comprising a first pad operatively connected to said emitter of the output transistor to operate as an output pad, and a second pad operatively connected to said base of the transistor of the ECL gate to operate as an input pad; a plurality of protective elements arranged in a vicinity of said input/output pads and of said high potential level power supply line, said protective elements comprising an NPN type transistor having a collector operatively connected to said high potential level power supply line, an emitter operatively connected to said input/output pads, and a base operatively connected to said input/output pad, said protective elements being conductive when a high electrostatic energy is applied to said input/output pads, for preventing destruction of said transistors of the ECl gate or said output transistors; wherein each of said output transistors and a corresponding one of said transistors of the protective elements are formed within the same collector land, and said high potential level power supply line extends over said collector land and is connected to said collector land, base regions of said protective transistors and output transistors are formed in said collector land respectively, emitter regions of said protective transistors and output transistors are formed in said base regions thereof respectively; and a low potential level power supply line being formed on said chip.