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EP0073641A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Integrated circuit device

Assignee: Fujitsu Ltd
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Filing: 1982-08-25
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Granted: —
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Expires: 2002-08-25
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Abstract

Abstract An integrated circuit device such as a gate array or a master slice LSI device which is formed on a semiconductor chip (1) and which comprises an inner cell array (8) including a plurality of inner cells (11), an outer cell array including a plurality of outer cells (7) formed around the inner cell array (8), a power supply portion (6) having one or more outer power supply lines, and a plurality of inner power supply lines (10) connected to the outer power supply lines and formed on the inner cell array (8). The ratio of the pitch of the outer cells (7) to the pitch of the inner power supply lines (10) or lines of the inner cells (11) is determined by the ratio of two integers. In the integrated circuit device, sets of outer (7) and inner (11) cells arranged in a predetermined positional relationship to each other are formed a plurality of times along the side of the semiconductor chip (1).

Inventors

  • 👤 Tetsu Tanizawa
  • 👤 Hitoshi Omichi
  • 👤 Yoshiharu Mitono

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-24 07:31
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17736; H03K19/17744; G; G11; G11C; G11C5/00; G11C5/02; G11C5/025; H03K19/1731; H03K19/1732; H03K19/1778; H03K19/17796; H10; H10D; H10D84/00; H10D84/90; H10D84/998; H10W; H10W72/00; H10W72/90; H10W72/921; H10W72/926; Y; Y10; Y10S; Y10S257/00; Y10S257/923

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 165 words
An integrated circuit device such as a gate array or master slice which is formed on a semiconductor chip (1) and which comprises an inner cell array (8) including a plurality of inner cells (11), an outer sell array including a plurality of outer cells (7) formed around the inner cell array (.8), a power supply portion (6) having one or more outer power supply lines, and a plurality of inner power supply lines (1) connected to the outer power supply lines and formed on the inner cell array (8), characterised in that the pitch P E of the outer cells (7) and the pitch P I of the inner cells (11) have the following relationship: mP E = nP I where m and n are both positive integers, and in that sets of outer (7) and inner (11) cells which are arranged in a predetermined positional relationship to each other are formed a plurality of times along a side of the semiconductor chip (1).
Claim 2
Dependent Claim 165 words
An integrated circuit device such as a gate array or master slice which is formed on a semiconductor chip (1) and which comprises an inner cell array (8) including a plurality of inner cells (11), an outer sell array including a plurality of outer cells (7) formed around the inner cell array (.8), a power supply portion (6) having one or more outer power supply lines, and a plurality of inner power supply lines (1) connected to the outer power supply lines and formed on the inner cell array (8), characterised in that the pitch P E of the outer cells (7) and the pitch P I of the inner cells (11) have the following relationship: mP E = nP I where m and n are both positive integers, and in that sets of outer (7) and inner (11) cells which are arranged in a predetermined positional relationship to each other are formed a plurality of times along a side of the semiconductor chip (1).
Claim 3
Dependent Claim 38 words
An integrated circuit device according to claim 1, wherein the number m is equal to or smaller than L/2, where L is a number of the outer cells (7) arranged along the side of the semiconductor chip (1).
Claim 4
Dependent Claim 30 words
An integrated circuit device according to claim 1 or 2, wherein the inner power supply lines (10) are arranged in a one-to-one correspondence with lines of the inner cells (11).
Claim 5
Dependent Claim 36 words
An integrated circuit device according to any one of the preceding claims, wherein the outer cells (7) and the inner cells (11) are interconnected by an interface pattern portion which comprises m different of interface patterns.
Claim 6
Dependent Claim 27 words
An integrated circuit device according to claim 4, wherein each of the interface pattern portions is integrally formed with the outer cell to form a macro cell.
Claim 7
Dependent Claim 39 words
An integrated circuit device according to any one of the preceding claims wherein the outer cells are arranged along a side of the semiconductor chip at a pitch almost equal to the pitch of bonding pads (5) for signals.
Claim 8
Dependent Claim 43 words
An integrated circuit device according to any one of the preceding claims, wherein the power supply portion (6) is formed over the area of the outer cells and/or of an interface pattern portion connecting the outer cells (7) and the inner cells (8).

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