Interrupt control circuit

Claim 2

An interrupt control circuit for a data processing unit which fetches and executes instructions for controlling an interrupt request signal from an external device which has an assigned interrupt level, said interrupt control circuit comprising: level storage means for storing interrupt-accept level data corresponding to each instruction and specifying the interrupt level of the interrupt request signal to be accepted for interrupt; first comparison means for reading, when an instruction is fetched for execution, the interrupt-accept level data corresponding to the instruction from said level storage means and for comparing the interrupt-accept level with the interrupt level of the interrupt request signal; and first acceptance means for accepting the interrupt request signal to initiate the interrupt function upon the comparing by said first comparison means.

Claim 3

An interrupt control circuit according to claim 1, wherein said level storage means stores the interrupt-accept level data which corresponds to a classification of the instruction.

Claim 4

An interrupt control circuit according to claim 1, wherein the interrupt-accept level data is set in said level storage means by a program.

Claim 5

An interrupt control circuit according to claim 1, further comprising: setting means for setting a number; loop detection means for detecting a loop of the instructions during execution of the instructions; count means for counting the loops detected by said loop detection means; second comparison means for comparing the number set by said setting means with the number of loops counted by said count means; and second acceptance means for accepting the interrupt request signal to initiate the interrupt function of the data processing unit upon the comparing by said second comparison means.

Claim 6

An interrupt control circuit for a data processing unit which has first buffer storage means for storing a plurality of instructions, the interrupt control circuit for controlling an interrupt request signal which is input from an external device which has an assigned interrupt level, said interrupt control circuit comprising: level storage means for storing interrupt-accept level data corresponding to an instruction and specifying the interrupt level of the interrupt request signal to be accepted for interrupt; transfer means for reading the interrupt-accept level data, from said level storage means, corresponding to the instruction stored in the first buffer storage means and for storing the interrupt-accept level data into an area of the first buffer storage means corresponding to the instruction; first comparison means for reading the interrupt-enable level data, from the first buffer storage means, corresponding to an instruction fetched from the first buffer storage means for execution and for comparing the interrupt-enable level with the interrupt level of the interrupt request signal; and first acceptance means for accepting the interrupt request signal to initiate the interrupt function of the data processing unit upon the comparing by said first comparison means.

Claim 7

An interrupt control circuit for a data processing unit which has first buffer storage means for storing a plurality of instructions, the interrupt control circuit for controlling an interrupt request signal which is input from an external device which has an assigned interrupt level, said interrupt control circuit comprising: level storage means for storing interrupt-accept level data corresponding to an instruction and specifying the interrupt level of the interrupt request signal to be accepted for interrupt; transfer means for reading the interrupt-accept level data, from said level storage means, corresponding to the instruction stored in the first buffer storage means and for storing the interrupt-accept level data into an area of the first buffer storage means corresponding to the instruction; first comparison means for reading the interrupt-enable level data, from the first buffer storage means, corresponding to an instruction fetched from the first buffer storage means for execution and for comparing the interrupt-enable level with the interrupt level of the interrupt request signal; and first acceptance means for accepting the interrupt request signal to initiate the interrupt function of the data processing unit upon the comparing by said first comparison means.

Claim 8

An interrupt control circuit according to claim 5, wherein said first buffer storage means stores a single instruction.

Claim 9

An interrupt control circuit according to claim 5, wherein said level storage means stores the interrupt-accept level data which corresponds to a classification of the instruction.

Claim 10

An interrupt control circuit according to claim 5, wherein the interrupt-accept level data is set in said level storage means by a program.

Claim 11

An interrupt control circuit according to claim 5, further comprising: setting means for setting a number; loop detection means for detecting a loop of the instructions during execution of the instructions; count means for counting the loops detected by said loop detection means; second comparison means for comparing the number set by said setting means with the number of loops counted by said count means; and second acceptance means for accepting the interrupt request signal to initiate the interrupt function of the data processing unit upon the comparing by said second comparison means.

Claim 12

An interrupt control circuit according to claim 9, wherein said first buffer storage means comprises a storage device which includes a plurality of entries, each entry having an entry number and storing an instruction and a next entry number which specifies the number of an entry whose instruction is to be executed next, and said loop detection means detects a loop when an entry includes the next entry number which is smaller than the entry number thereof.

Claim 15

A method according to claim 11, further comprising: (g) setting a number; (h) detecting a loop of the instructions during execution of the instructions; (i) counting the loops detected in step (h); (j) comparing the number set in step (g) with the number of loops counted in step (i); and (k) accepting the interrupt request signal to initiate the interrupt function of the data processing unit in dependence upon the comparison in step (j).

Claim 18

A method according to claim 13, further comprising: (g) setting a number; (h) detecting a loop of the instructions during execution of the instructions; (i) counting the loops detected in step (h); (j) comparing the number set in step (g) with the number of loops counted in step (i); and (k) accepting the interrupt request signal to initiate the interrupt function of the data processing unit in dependence upon the comparison in step (j).