Multi-task control device for central processor task execution control provided as a peripheral device and capable of prioritizing and timesharing the tasks

Claim 1

A multi-task control device for a computer system in which a single central processor is used and said multi-task control device is connected to said single central processor via a bus, said multi-task control device controlling a plurality of tasks to be executed by said single central processor, comprising: a plurality of task control block memory areas for storing data related to each of said plurality of tasks, said data including a priority order, a memory address, and the status of a task; means for selectively receiving commands for the controlling of a plurality of tasks to be executed from said single central processor; and control means, responsive to said commands for the controlling of a plurality of tasks from said means for receiving, for comparing the priority orders of said tasks to be executed stored in said task control block memory areas; said control means arraying said tasks to be executed in the order of their respective priorities; said control means generating an interrupt signal to said central processor for the execution of a task with highest priority; said control means conducting a time-sharing process for the execution of a number of tasks having equivalent priority orders; said control means suspending the execution of a task when necessary for the execution of an external event; said control means reactivating the execution of a suspended task upon completion of said external event; said control means changing the priority order of a task in its corresponding task control block memory area; said control means clearing the task control block memory area of a task to be deleted; said control means specifying a task control block memory area of a task to be generated; and said multi-task control device being provided as a peripheral device of said computer system.