Monitor for priority level of task in information processing system

Claim 2

In a data processing where a number of tasks share a central processing unit according to a plurality of priority levels, a priority level monitor comprising: a control register coupled to said central processing unit for receiving from said central processing unit signals indicating the beginning of the execution of a task, the completion of the execution of that task and the priority level associated with that task and for storing said signals; a priority level timer connected to said control register for measuring the execution time of each task processed by said central processing unit and for generating an overflow signal when the execution time of a task exceeds a predetermined permissible execution time allowed to tasks having the priority level of said task; and an interrupt signal generator connected to said priority level timer and said central processing unit for generating an interrupt signal and transmitting said interrupt signal to said central processing unit when said priority level timer generates said overflow signal, whereby said apparatus monitors the execution time of tasks assigned to each priority level and causes a task to be aborted when the execution time of the task exceeds a predetermined permissible execution time allowed to tasks of that priority level.

Claim 3

A priority level monitor as claimed in claim 1, wherein said control register further comprises an interrupt clear signal generating means for generating an interrupt clear signal when said central processing unit resumes execution after an interrupt; said interrupt signal generator is further connected to said interrupt clear signal generating means; and said priority level timer comprises: a clock pulse generator for generating clock pulses; a plurality of priority level execution time measurement circuits each corresponding to one of the plurality of priority levels having a clock pulse input terminal for receiving clock pulses, a clock pulse output terminal for producing clock pulses, a flip-flop circuit connected to said control register for assuming a first state during the execution of a task havig the corresponding priority level and for assuming a second state upon completion of a task having the corresponding priority level, a first AND gate having a first input connected to said clock pulse input terminal, a second input connected to said flip-flop circuit, and an output for coupling the signals received on said first input to said output when said flip-flop circuit is in said first state, a counter connected to said output of said first AND gate for producing said overflow signal when a predetermined number of clock pulses are received, and a second AND gate having a first input connected to said clock pulse input terminal, a second input connected to said flip-flop circuit, and an output connected to said clock pulse output terminal for coupling the signals received on said first input to said clock pulse output terminal when said flip-flop circuit is in said second state, said priority level execution time measurement corresponding to the highest priority level having said clock pulse input terminal connected to said clock pulse generator and said priority level execution time measurement circuits corresponding to lower priority levels having said clock pulse input terminal connected to said clock pulse output terminal of said priority level execution time measurement circuit corresponding to the next higher priority; and wherein said interrupt signal generator comprises: an OR circuit having a plurality of inputs one connected to each of said counters of said priority level execution time measuring circuit for producing an OR output signal when any of said counters of said priority level execution time measuring circuits produce said overflow signal; and a flip-flop circuit connected to said OR circuit and said interrupt clear signal generating means for assuming a first state and generating said interrupt signal upon receiving said OR output signal and for assuming a second state and ceasing generation of said interrupt signal upon receiving said interrupt clear signal.

Claim 4

A priority level monitor as claimed in claim 1, wherein said control register further comprises: a priority level counter clearing means connected to said counters of said priority level execution time measurement circuits for resetting said counter of said priority level execution time measurement circuit when a task having the corresponding priority level is completed.

Claim 5

A priority level monitor as claimed in claim 1, further comprising: a total execution time measuring means connected to said control register for measuring the total execution time of tasks in each priority level and for producing a timing signal whenever the execution time of a particular priority level exceeds an integral multiple of a corresponding predetermined period; and a timing interrupt signal generator connected to said total execution time measuring means and the central processing unit for generating a timing interrupt signal and transmitting said timing interrupt signal to the central processing unit when said total execution time measuring means generates said timing signal.

Claim 6

A priority level monitor as claimed in claim 3, wherein said total execution time measuring means comprises: a plurality of level counters each corresponding to one of the priority levels and one of said priority level execution time measurement circuits connected to the output of said first AND gate for counting the clock pulses received therefrom and producing said timing signal whenever an integral multiple of a predetermined number of clock pulses are received; and said timing interrupt signal generator comprises: an OR circuit having a plurality of inputs one connected to each of said level counters of said total execution time measuring means for prodcuing an OR output signal when any of said level counters of said total execution time measuring means produces a timing signal; and a flip-flop circuit connected to said OR circuit and said interrupt clear signal generating means for assuming a first state and generating said timing interrupt signal upon receiving said OR output signal and for assuming a second state and ceasing generation of said timing interrupt signal upon receiving said interrupt clear signal.