Interrupt test circuit for microprocessor system

Claim 2

A digital data processing system comprising: a central processing unit: an interrupt controller having a request signal input for controlling execution of an interrupt operation of said central processing unit in response to an interrupt request signal; a peripheral unit having a request signal output for providing an interrupt request signal to the request signal input of the interrupt controller; and a n interrupt test circuit, said interrupt test circuit including: test signal input circuitry connected to a test signal input to receive an interrupt test signal, the test signal input circuitry is not coupled to the request signal output of the peripheral unit; test signal output circuitry connected to the request signal input of the interrupt controller, and storage means having an input coupled to the test signal input circuitry for storing the interrupt request test signal when receiving a first control signal at a control signal input, and having an output coupled to the test signal output circuitry for supplying the interrupt test signal through the test signal output circuitry to the request signal input of the interrupt controller.

Claim 3

A digital data processing system according to claim 1 wherein said control signal input of said storage means is coupled to an output of the central processing unit.

Claim 4

A digital data processing system according to claim 1 further comprising a data bus coupled to the central processing unit and to the test signal input circuitry of the interrupt test circuit.

Claim 5

A digital data processing system according to claim 1 wherein said test signal output circuitry further comprises an input coupled to the interrupt request signal output of the peripheral unit and means for transmitting the interrupt request signal received from the peripheral unit to the interrupt controller when the interrupt request signal is received.

Claim 6

A digital data processing system according to claim 4 wherein said interrupt test circuit further comprises an OR gate having two inputs receiving the interrupt request signal from the peripheral unit and the test signal from the storage means respectively, and having one output connected to the request signal input of the interrupt controller.

Claim 7

A digital data processing system according to claim 4 wherein said interrupt test circuit further comprises gate means having an input connected to the request signal output of the peripheral unit for sensing the request signal under control of the central processing unit.

Claim 8

A digital data processing system according to claim 6 wherein said gate means transmits the request signal to a data bus when receiving a read signal from the central processing unit.

Claim 9

A digital data processing system including, a central processing unit, an interrupt controller included in the central processing unit and having a request signal input, for controlling execution of an interrupt operation of said central processing unit in response to an interrupt request signal, a plurality of peripheral units each having a request signal output for providing an interrupt request signal, and a plurality of interrupt test circuits, each of said interrupt test circuits being connected between the request signal output of one of the peripheral units and the interrupt controller, and receiving the interrupt request signal from the corresponding peripheral unit for transmitting the interrupt request signal to the interrupt controller, each of said interrupt test circuits comprising: a test signal output connected to the request signal input of the interrupt controller; a register means having a write signal input for receiving a write signal from the central processing unit, and having a test signal input for receiving a test signal, the test signal input is not coupled to any of the request signal outputs of the peripheral units, said register means stores the test signal when receiving the write signal and supplies the test signal to an output of the register means; an OR gate having two inputs receiving the interrupt request signal from the one of the peripheral units and the test signal from the output of the register means respectively, and having one output connected to the test signal output.

Claim 10

A digital data processing system including, a central processing unit, an interrupt controller included in the central processing unit and having a request signal input, for controlling execution of an interrupt operation of said central processing unit in response to an interrupt request signal, a plurality of peripheral units each having a request signal output for providing an interrupt request signal, and a plurality of interrupt test circuits, each of said interrupt test circuits being connected between the request signal output of one of the peripheral units and the interrupt controller, and receiving the interrupt request signal from the corresponding peripheral unit for transmitting the interrupt request signal to the interrupt controller, each of said interrupt test circuits comprising: a test signal output connected to the request signal input of the interrupt controller; a register means having a write signal input for receiving a write signal from the central processing unit, and having a test signal input for receiving a test signal, the test signal input is not coupled to any of the request signal outputs of the peripheral units, said register means stores the test signal when receiving the write signal and supplies the test signal to an output of the register means; an OR gate having two inputs receiving the interrupt request signal from the one of the peripheral units and the test signal from the output of the register means respectively, and having one output connected to the test signal output.

Claim 11

A digital data processing system comprising: a data bus; a central processing unit coupled to the data bus and having an interrupt request input; a peripheral unit having an interrupt request output; and an interrupt test circuit having a write control input, the interrupt test circuit further comprising: storage means coupled to the data bus and to the write control input for storing a data value received from the data bus when a first control signal is received at the write control input, the storage means having an output; and interrupt signal generator means having an input coupled to the interrupt request output of the peripheral, an input coupled to the output of the storage means and having an output coupled to the interrupt request input of the central processing unit for generating an interrupt request signal when an interrupt request signal is received from the peripheral unit or when the output of the storage means is in a first state.

Claim 12

A digital data processing system comprising: a data bus; a central processing unit coupled to the data bus and having an interrupt request input; a peripheral unit having an interrupt request output; and an interrupt test circuit having a write control input, the interrupt test circuit further comprising: storage means coupled to the data bus and to the write control input for storing a data value received from the data bus when a first control signal is received at the write control input, the storage means having an output; and interrupt signal generator means having an input coupled to the interrupt request output of the peripheral, an input coupled to the output of the storage means and having an output coupled to the interrupt request input of the central processing unit for generating an interrupt request signal when an interrupt request signal is received from the peripheral unit or when the output of the storage means is in a first state.

Claim 13

A digital data processing system according to claim 9 wherein the central processing unit is coupled to provide the first control signal to the write control input of the interrupt test circuit.

Claim 14

A digital data processing system according to claim 10 wherein the central processing unit provides the data value to the data bus.

Claim 15

A digital data processing system according to claim 9 wherein the interrupt test circuit has a read control input and further comprises: read means having an input coupled to the output of the interrupt signal generator means, an input coupled to the read control input and an output coupled to the data bus for providing an output signal having a value determined by the output of the interrupt signal generator means to the data bus when a second control signal is received at the read control input.

Claim 16

A digital data processing system according to claim 12 wherein the central processing unit is coupled to provide the first and second control signals to the write control input and read control input, respectively, of the interrupt test circuit.

Claim 17

A digital data processing system according to claim 13 wherein the central processing unit provides the data value to the data bus and receives the output signal from the data bus.