Patent US5612893A successfully refreshed from Google Patents.
US5612893A
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Method and apparatus for compacting integrataed circuits with transistor sizing
Assignee: Philips Semiconductors Inc
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Filing: 1996-05-24
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Granted: 1997-03-18
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Expires: 2016-05-24
Abstract
Abstract A computer-aided design method and apparatus for compacting semiconductor circuit layouts to meet a specified set of design rules begins by fracturing a specified circuit layout into a set of trapezoids and storing the resulting cells in a database identifying the boundaries of each cell, and the cell adjacent each boundary. Nonempty cells are identified as being of specific materials, and empty spaces between cells are represented in the database. For each cell boundary, the database also stores data representing the boundary edge's end points. Neighboring cells on the same and related layers of the circuit layout share edges in the database. When a point on an edge of a cell is moved, the edge of each neighboring cell that shares that point is also moved. However, the method sizes gate cells of transistors differently from other cells by maintaining the former at predetermined dimensions, with a user-definable override to resize transistors to a percentage of the predetermined dimensions.
Inventors
- 👤 Ling-Hui Hao
- 👤 Lawrence B. Edwards
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:39
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/398
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
91 words
A method executed by a computer under the control of a program, said computer including a memory for storing said program, said method comprising the steps of: receiving input data representing a semiconductor mask pattern for an integrated circuit layout; invoking a set of compaction design rules to be satisfied by said semiconductor mask pattern; identifying transistor gate cells within said semiconductor mask pattern; compacting said semiconductor mask pattern, including individual cells of said semiconductor mask pattern, except said transistor gate cells, in accordance with said set of compaction design rules.
Claim 2
Independent Claim
91 words
A method executed by a computer under the control of a program, said computer including a memory for storing said program, said method comprising the steps of: receiving input data representing a semiconductor mask pattern for an integrated circuit layout; invoking a set of compaction design rules to be satisfied by said semiconductor mask pattern; identifying transistor gate cells within said semiconductor mask pattern; compacting said semiconductor mask pattern, including individual cells of said semiconductor mask pattern, except said transistor gate cells, in accordance with said set of compaction design rules.
Claim 3
Dependent Claim
37 words
The method of claim 1 further comprising the step of: applying a transistor scaling value to said transistor gate cells of said semiconductor mask pattern so as to maintain predetermined minimum dimensions for said transistor gate cells.
Claim 4
Dependent Claim
95 words
A computer readable memory that can be used to direct a computer to function in a specified manner, comprising: a first set of executable instructions including a set of compaction design rules to be satisfied by a semiconductor mask pattern of an integrated circuit layout; a second set of executable instructions to identify transistor gate cells within said semiconductor mask pattern; a third set of executable instructions to compact said semiconductor mask pattern, including individual cells of said semiconductor mask pattern, except said transistor gate cells, in accordance with said set of compaction design rules.
Claim 5
Dependent Claim
95 words
A computer readable memory that can be used to direct a computer to function in a specified manner, comprising: a first set of executable instructions including a set of compaction design rules to be satisfied by a semiconductor mask pattern of an integrated circuit layout; a second set of executable instructions to identify transistor gate cells within said semiconductor mask pattern; a third set of executable instructions to compact said semiconductor mask pattern, including individual cells of said semiconductor mask pattern, except said transistor gate cells, in accordance with said set of compaction design rules.
Claim 6
Dependent Claim
43 words
The computer readable memory of claim 3 further comprising a fourth set of executable instructions to apply a transistor scaling value to said transistor gate cells of said semiconductor mask pattern so as to maintain predetermined minimum dimensions for said transistor gate cells.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-17 | 2000-09-16 | 2001-03-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-17 | 2004-09-16 | 2005-03-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-17 | 2008-09-16 | 2009-03-18 | $7700.00 | Window Closed / Lapsed |