US5473547A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic synthesizer for engineering changes
Assignee: Fujitsu Ltd
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Filing: 1992-10-26
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Granted: 1995-12-05
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Expires: 2012-10-26
Abstract
Abstract A synthesizer of logic networks of computers that has a capability of handling engineering changes necessitated by changing transistor circuits is disclosed. In order to design a computer, a computer system is designed first, and then the design of logic networks follows. Then transistor circuits are designed and then actually realized with transistors and other electronic components. But very often, transistor circuits need to be partly changed for various reasons. Responding to these engineering changes, the disclosed logic synthesizer can with great ease synthesize a new logic network such that the transistor circuit corresponding to this new logic network has necessary engineering changes made and keeps intact the portion of the original transistor circuit that the user of this synthesizer does not want to change.
Inventors
- 👤 Saburo Muroga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 02:15
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/327
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
149 words
A method for conducting logic network synthesis comprising: converting a transistor circuit having transistor gates into a logic network, each single transistor gate in the transistor circuit being converted to a corresponding single logic gate having an output function identical to that of the transistor gate from which it was converted; specifying a first portion of the logic network which requires engineering changes, a second portion corresponding to a portion of the transistor circuit to be kept intact, and a third portion including the logic network outside of said first and second portions; converting the first portion of the logic network to make said engineering changes; and producing a new transistor circuit from said first portion to which changes were made and said second and third portions while recovering network functions that were modified as a result of said making changes to said first portion of the logic network.
Claim 2
Independent Claim
149 words
A method for conducting logic network synthesis comprising: converting a transistor circuit having transistor gates into a logic network, each single transistor gate in the transistor circuit being converted to a corresponding single logic gate having an output function identical to that of the transistor gate from which it was converted; specifying a first portion of the logic network which requires engineering changes, a second portion corresponding to a portion of the transistor circuit to be kept intact, and a third portion including the logic network outside of said first and second portions; converting the first portion of the logic network to make said engineering changes; and producing a new transistor circuit from said first portion to which changes were made and said second and third portions while recovering network functions that were modified as a result of said making changes to said first portion of the logic network.
Claim 3
Dependent Claim
17 words
The method of claim 5 wherein: said recovering of functions is accomplished by pruning and network transformation.
Claim 4
Dependent Claim
19 words
The logic synthesizer of claim 5, wherein: the complexity of logic gates is controlled during execution of said method.
Claim 5
Independent Claim
130 words
A method for conducting logic network synthesis comprising: converting a transistor circuit having transistor gates into a logic network, each transistor gate in the transistor circuit being converted to a corresponding single logic gate having an output function identical to that of the transistor gate from which it was converted; specifying a first portion of the logic network which requires engineering changes, a second portion corresponding to a portion of the transistor circuit to be kept intact, and a third portion including the logic network outside of said first and second portions; converting the first portion of the logic network to make said engineering changes; and reducing the third portion of the logic network while recovering functions of the logic network which may have changed during said step of converting.
Claim 6
Independent Claim
130 words
A method for conducting logic network synthesis comprising: converting a transistor circuit having transistor gates into a logic network, each transistor gate in the transistor circuit being converted to a corresponding single logic gate having an output function identical to that of the transistor gate from which it was converted; specifying a first portion of the logic network which requires engineering changes, a second portion corresponding to a portion of the transistor circuit to be kept intact, and a third portion including the logic network outside of said first and second portions; converting the first portion of the logic network to make said engineering changes; and reducing the third portion of the logic network while recovering functions of the logic network which may have changed during said step of converting.
Claim 7
Dependent Claim
31 words
The method of claim 4, further comprising: technology mapping said third portion, subsequent to said reducing and prior to said producing, to create a final logic network for said third portion.
Claim 8
Dependent Claim
26 words
The method of claim 4, wherein: said reducing includes modification of connections between logic gates in the second portion and logic gates in the third portion.
Claim 9
Dependent Claim
28 words
The method of claim 6, wherein: said modification of connections includes deletion of connections between logic gates in the second portion and logic gates in the third portion.
Claim 10
Dependent Claim
28 words
The method of claim 6, wherein: said modification of connections includes addition of connections between logic gates in the second portion and logic gates in the third portion.
Claim 11
Dependent Claim
13 words
The method of claim 4, wherein: said reducing includes pruning and network transformation.
Claim 12
Dependent Claim
19 words
The logic synthesizer of claim 4, wherein: the complexity of logic gates is controlled during execution of said method.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-04 | 1999-06-05 | 1999-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-04 | 2003-06-05 | 2003-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-04 | 2007-06-05 | 2007-12-05 | $7700.00 | Window Closed / Lapsed |