Programmable logic array integrated circuits with enhanced output routing

Claim 2

A configurable electronic device comprising: a plurality of logic blocks, at least one logic block comprising outputs to other logic blocks, an array of internal interconnection lines within said block programmably connected to inputs of said block, said at least one logic block performing selected logical operations; a general interconnect structure programmably connecting the outputs of said logic blocks to said array of internal interconnection lines of another of said logic blocks; an output pin interconnect line, said output pin interconnect line directly programmably connected to said internal interconnection lines without being routed through said general interconnect or any other of said logic blocks and connected directly to an output pin of said configurable logic device.

Claim 3

The configurable electronic device according to claim 1 wherein said logic blocks are comprised of a plurality of look-up tables.

Claim 4

The configurable electronic device according to claim 1 wherein said general interconnect structure comprises a plurality rows and columns of conductors.

Claim 5

The configurable electronic device according to claim 2 wherein data in said look-up tables is stored in static random access memory.

Claim 6

The configurable electronic device according to claim 1 further comprising a plurality of multiplexers with inputs connected to said general interconnect structure and outputs connected to said array of internal interconnection lines.

Claim 7

The configurable electronic device as recited in claim 1 further comprising an output driver on said output pin interconnect line.

Claim 8

The configurable electronic device as recited in claim 1 wherein said general interconnect structure comprises an array of vertical and horizontal interconnect lines between said logic blocks.

Claim 9

The configurable electronic device as recited in claim 1 further comprising a plurality of carry chain interconnections said carry chain interconnections programmably connected between carry outputs of one logic block to carry inputs of another logic block forming a carry chain for add operations.

Claim 10

The configurable electronic device as recited in claim 1 further comprising cascade connect conductors said cascade conductors logically connecting outputs of a logic element to outputs of an adjacent logic element.

Claim 11

The configurable electronic device as recited in claim 1 wherein said array of internal interconnection lines is fully populated to inputs of individual logic elements in said logic block and to said output pin interconnect line.

Claim 12

The configurable electronic device as recited in claim 1 wherein the configurable electronic device is connected to a system, said system comprising: a processing unit operationally connected to; a memory; and to an input/output interface connecting said system to input and output devices.

Claim 13

A programmable logic device comprising: a plurality of logic array blocks (LABs), at least one LAB comprising a plurality of inputs and outputs and capable of performing a logic function such that said at least one LAB's outputs represent a logical function of its inputs; a general interconnect structure capable of routing the outputs of one of said LABs to the inputs of another of said LABs; at least one LAB-based interconnect, each LAB-based interconnect associated with a particular LAB capable of connecting selected lines of said general interconnect to selected input lines of said LAB; wherein said at least one LAB-based interconnect associated with at least one LAB includes a plurality of output lines connectable to a device I/O pin, said output line directly programmably connected to said LAB-based interconnect without being routed through said general interconnect or any other of said LABs.

Claim 14

A programmable logic device comprising: a plurality of logic array blocks (LABs), at least one LAB comprising a plurality of inputs and outputs and capable of performing a logic function such that said at least one LAB's outputs represent a logical function of its inputs; a general interconnect structure capable of routing the outputs of one of said LABs to the inputs of another of said LABs; at least one LAB-based interconnect, each LAB-based interconnect associated with a particular LAB capable of connecting selected lines of said general interconnect to selected input lines of said LAB; wherein said at least one LAB-based interconnect associated with at least one LAB includes a plurality of output lines connectable to a device I/O pin, said output line directly programmably connected to said LAB-based interconnect without being routed through said general interconnect or any other of said LABs.

Claim 15

A programmable logic device as recited in claim 12 wherein said LABs are comprised of a number of look-up tables.

Claim 16

A programmable logic device as recited in claim 12 wherein said general interconnect structure comprises a plurality rows and columns of conductors.

Claim 17

A programmable logic device as recited in claim 12 wherein data in said look-up tables is stored in static random access memory.

Claim 20

A configurable logic device comprising: a plurality of logic array blocks (LABs), arranged in a plurality of rows and columns, at least one LAB having a plurality of inputs and outputs and capable of performing a logic function such that said at least one LAB's outputs represent a logical function of its inputs, said logic function being programmable during chip manufacture or use; a general interconnect structure comprising a plurality of rows of conductors and a plurality of columns of conductors, said interconnect structure capable of routing select signals between said columns of conductors and said rows of conductors; LAB output lines for selectively connecting said LAB outputs to said rows or said columns of conductors; at least one LAB-based input interconnect associated with a particular LAB capable of connecting selected lines of said general interconnect to selected input lines of said LAB; wherein said at least one LAB-based interconnect associated with at least one LAB includes a plurality of output lines connectable to a device I/O pin without being routed through a logic element in said LAB.

Claim 21

A configurable logic device comprising: a plurality of logic array blocks (LABs), arranged in a plurality of rows and columns, at least one LAB having a plurality of inputs and outputs and capable of performing a logic function such that said at least one LAB's outputs represent a logical function of its inputs, said logic function being programmable during chip manufacture or use; a general interconnect structure comprising a plurality of rows of conductors and a plurality of columns of conductors, said interconnect structure capable of routing select signals between said columns of conductors and said rows of conductors; LAB output lines for selectively connecting said LAB outputs to said rows or said columns of conductors; at least one LAB-based input interconnect associated with a particular LAB capable of connecting selected lines of said general interconnect to selected input lines of said LAB; wherein said at least one LAB-based interconnect associated with at least one LAB includes a plurality of output lines connectable to a device I/O pin without being routed through a logic element in said LAB.

Claim 22

The configurable logic device of claim 17 wherein said LAB-based input interconnect is a fully populated interconnection between inputs to logic circuits of said LAB and outputs of a plurality of multiplexers, said multiplexers having their inputs connected to conductors in said general interconnect.

Claim 23

The configurable logic device of claim 18 wherein the outputs of said multiplexers are selected by a programmable store.

Claim 24

The configurable logic device of claim 19 wherein the programmable store is an SRAM cell.

Claim 25

The configurable logic device of claim 17 wherein the LABs are comprised of a plurality of look-up tables.

Claim 26

The configurable logic device of claim 17 wherein each output of an LAB is connectable to a limited number of lines in said general interconnect and to a feedback input back into said LAB interconnect.

Claim 27

The configurable logic device of claim 17 further comprising a plurality of carry chain interconnections.

Claim 28

The configurable logic device of claim 17 further comprising a plurality of cascade connect conductors.

Claim 29

A logic array block (LAB) for use in a configurable logic device comprising: a plurality of LAB-input lines for receiving signals; a plurality of logic elements (LEs) each having an output and each having a plurality of LE-input lines, said LE-input lines being programmably connectable to said LAB-input lines; and a plurality of device-output lines, said device-output lines being programmably connectable to said LAB-input lines without being routed through any LE.

Claim 30

A logic array block (LAB) for use in a configurable logic device comprising: a plurality of LAB-input lines for receiving signals; a plurality of logic elements (LEs) each having an output and each having a plurality of LE-input lines, said LE-input lines being programmably connectable to said LAB-input lines; and a plurality of device-output lines, said device-output lines being programmably connectable to said LAB-input lines without being routed through any LE.

Claim 31

The apparatus according to claim 25 wherein each of said device-output lines is programmably connectable to said LAB-input lines through an output line multiplexer, said output line multiplexer controlled by a programmable store.

Claim 32

A digital information processing system comprising: a main processor operationally connected to; an input device; an output device; a memory; and at least one programmable logic device comprising: a plurality of logic blocks, at least one logic block comprising outputs to other logic blocks, an array of internal interconnection lines within said block, said at least one logic block performing selected logical operations; a general interconnect structure programmably connecting the outputs of said logic blocks to said array of internal interconnection lines of another of said logic blocks; and an output pin interconnect line, said output pin interconnect line directly programmably connected to said internal interconnection lines without being routed through any logic devices within said logic block and connected directly to an output pin of said configurable logic device.

Claim 33

A digital information processing system comprising: a main processor operationally connected to; an input device; an output device; a memory; and at least one programmable logic device comprising: a plurality of logic blocks, at least one logic block comprising outputs to other logic blocks, an array of internal interconnection lines within said block, said at least one logic block performing selected logical operations; a general interconnect structure programmably connecting the outputs of said logic blocks to said array of internal interconnection lines of another of said logic blocks; and an output pin interconnect line, said output pin interconnect line directly programmably connected to said internal interconnection lines without being routed through any logic devices within said logic block and connected directly to an output pin of said configurable logic device.

Claim 34

The digital information processing system of claim 27 wherein said logic blocks are comprised of a plurality of look-up tables and wherein said general interconnect structure comprises a plurality rows and columns of conductors and wherein data in said look-up tables is stored in static random access memory and further comprising a plurality of multiplexers with inputs connected to said general interconnect structure and outputs connected to said array of input interconnections.