US5603009A
Expired / Lapsed
US
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Semiconductor memory device including a data transfer circuit for transferring data between a DRAM and an SRAM
Assignee: Renesas Electronics Corp
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Filing: 1994-12-14
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Granted: 1997-02-11
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Expires: 2014-12-14
Abstract
Abstract A semiconductor memory device containing a cache includes a static random access memory (SRAM) as a cache memory, and a dynamic random access memory (DRAM) as a main memory. Collective transfer of data blocks is possible between the DRAM and the SRAM through a bi-directional data transfer gate circuit and through an internal data line. A DRAM row decoder and a DRAM column decoder are provided in the DRAM. A SRAM row decoder and an SRAM column decoder are provided in the SRAM. Addresses of the SRAM and DRAM can be independently applied. The data transfer gate includes a latch circuit for latching data from the SRAM, which serves as a high speed memory, an amplifier circuit and a gate circuit for amplifying data from the DRAM, which serves as a large capacity memory, and for transmitting the amplified data to the SRAM, and a gate circuit, responsive to a DRAM write enable signal for transmitting write data to corresponding memory cells of the DRAM. After the data of the SRAM has been latched by a latch circuit, write data is transmitted from the gate circuit to the DRAM, and the write data is transmitted to the SRAM through the amplifier circuit and the gate circuit.
Inventors
- 👤 Yasuhiro Konishi
- 👤 Katsumi Dosaka
- 👤 Kouji Hayano
- 👤 Masaki Kumanoya
- 👤 Akira Yamazaki
- 👤 Hisashi Iwamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 07:26
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/02; G11C11/04; G11C7/00; G11C7/10; G11C7/1006; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0893; G11C11/005; G11C7/1015; G11C7/103; G11C7/1045; G11C2207/00; G11C2207/22; G11C2207/2254
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
169 words
A semiconductor device, comprising: a first memory cell array including a plurality of memory cells; a second memory cell array including a plurality of memory cells provided separate from said first memory cell array; data transfer means, provided between said first memory cell array and said second memory cell array, for transferring data between a selected memory cell of said first memory cell array and a selected memory cell of said second memory cell array, said data transfer means including: (a) first circuitry for transferring data received from said first memory cell array to said second memory cell array, and (b) second circuitry for transferring data received from said second memory cell array to said first memory cell array, said first and second circuitry provided in parallel with each other between said first and second memory cell arrays and having no common circuit elements; and control means for generating a data transfer control signal activating said first circuitry and said second circuitry in response to a transfer instruction signal.
Claim 2
Dependent Claim
169 words
A semiconductor device, comprising: a first memory cell array including a plurality of memory cells; a second memory cell array including a plurality of memory cells provided separate from said first memory cell array; data transfer means, provided between said first memory cell array and said second memory cell array, for transferring data between a selected memory cell of said first memory cell array and a selected memory cell of said second memory cell array, said data transfer means including: (a) first circuitry for transferring data received from said first memory cell array to said second memory cell array, and (b) second circuitry for transferring data received from said second memory cell array to said first memory cell array, said first and second circuitry provided in parallel with each other between said first and second memory cell arrays and having no common circuit elements; and control means for generating a data transfer control signal activating said first circuitry and said second circuitry in response to a transfer instruction signal.
Claim 3
Dependent Claim
24 words
The semiconductor device according to claim 1, wherein said first means includes latch means for latching data received from said first memory cell array.
Claim 4
Dependent Claim
25 words
The semiconductor device according to claim 1, wherein said second means includes an amplifier means for amplifying data received from said second memory cell array.
Claim 5
Dependent Claim
35 words
The semiconductor device according to claim 1, wherein said first memory cell array comprises a static random access memory (SRAM) array and said second memory cell array comprises a dynamic random access memory (DRAM) array.
Claim 6
Dependent Claim
22 words
The semiconductor device according to claim 1, wherein said first and second circuitry each include a driver for unidirectionally transferring received data.
Claim 7
Dependent Claim
144 words
The semiconductor memory device according to claim 1, wherein said second memory cell array comprises a plurality of memory blocks arranged in rows and columns, each of said memory blocks including a plurality of dynamic memory cells arranged in rows and columns, said memory blocks further arranged in a plurality of groups each comprising a row or a column of memory blocks; said second memory cell array further comprising: a plurality of first data transmitting means each coupled to a respective one of said memory blocks for transferring data to and from a selected memory cell of a corresponding memory block, and a second data transmitting means provided common to each of said plurality of groups of memory blocks for coupling a selected one of said plurality of first data transmitting means to said data transfer means in response to a group selection signal.
Claim 8
Dependent Claim
117 words
The semiconductor memory device according to claim 6, wherein each of said plurality of first data transmitting means comprises two first transmitting lines provided for each of said memory blocks, said second data transmitting means comprises two transmitting lines provided for each group, and wherein said semiconductor memory device further comprises first selecting means comprising: column selecting means for selecting two columns from a selected one of said memory blocks in accordance with an applied address, and means responsive to a block selecting signal generated in accordance with said applied address for connecting the two first transmitting lines provided for the selected one of said memory blocks to the two second transmitting lines of a corresponding group.
Claim 9
Dependent Claim
211 words
A semiconductor device, comprising: a first memory cell array including a plurality of memory cells; a second memory cell array including a plurality of memory cells provided separate from said first memory cell array; data transfer means provided between said first memory cell array and said second memory cell array for transferring data between a selected memory cell of said first memory cell array and a selected memory cell of said second memory cell array, said data transfer means including: (a) first circuitry for transferring data received from said first memory cell array to said second memory cell array, said first circuitry including a first storage means for temporarily retaining applied data, (b) second circuitry for transferring data received from said second memory cell array to said first memory cell array, said second circuitry including second storage means for retaining applied data temporarily, a data transfer path of said first circuitry being different from and in parallel with a data transfer path of said second circuitry, said first and second circuitry provided between said first and said second memory cell arrays and having no common component; and control means for generating a data transfer control signal activating said first circuitry and said second circuitry in response to a transfer instruction signal.
Claim 10
Dependent Claim
211 words
A semiconductor device, comprising: a first memory cell array including a plurality of memory cells; a second memory cell array including a plurality of memory cells provided separate from said first memory cell array; data transfer means provided between said first memory cell array and said second memory cell array for transferring data between a selected memory cell of said first memory cell array and a selected memory cell of said second memory cell array, said data transfer means including: (a) first circuitry for transferring data received from said first memory cell array to said second memory cell array, said first circuitry including a first storage means for temporarily retaining applied data, (b) second circuitry for transferring data received from said second memory cell array to said first memory cell array, said second circuitry including second storage means for retaining applied data temporarily, a data transfer path of said first circuitry being different from and in parallel with a data transfer path of said second circuitry, said first and second circuitry provided between said first and said second memory cell arrays and having no common component; and control means for generating a data transfer control signal activating said first circuitry and said second circuitry in response to a transfer instruction signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-11 | 2000-08-12 | 2001-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-11 | 2004-08-12 | 2005-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-11 | 2008-08-12 | 2009-02-11 | $7700.00 | Window Closed / Lapsed |