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JPS6339057A Expired / Lapsed JP ⏱️ 0.0 years remaining

Virtual storage memory

Assignee: Fujitsu Ltd
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Filing: 1986-08-05
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Granted: —
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Expires: 2006-08-05
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Abstract

Abstract PURPOSE:To transfer the block data with no use of a common data bus by storing a cache memory into the same chip as a main memory. CONSTITUTION:A cache memory CM and a main memory MM are mounted on the same semiconductor substrate. The word lines WL of both memories CM and MM are set in the same direction with the bit lines BL set so that the ends of these lines BL are set opposite to each other. A transfer gate TG is arranged between the CM and the MM and each element of the gate TG connects the corresponding bit lines of the CM and the MM together and releases these lines. Thus it is possible to transfer the block data to the CM from the MM within a chip even though the working data varied due to a fact that the operation jumps to a subroutine while a CPU is executing a program.

Inventors

  • 👤 Takashi Horii
  • 👤 堀井 孝

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 05:18
CPC Classifications
—

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