Set associative memory

Claim 2

A memory comprising: a memory array logically arranged as rows and columns of storage elements addressable by row addresses, each element being capable of storing a single bit of data, each row of storage elements being directly accessible independent of other rows; means responsive to row addresses received by memory for directly addressing rows of storage elements of the array for storage of rows in data buffers; a plurality of data buffers, each data buffer being connected to the memory array to receive and store a row of data from any addressed row of the array and to provide data as an output of the memory; means for selecting one of the data buffers to receive and store data from the memory array; means responsive to a column address for addressing bits within a selected data buffer to access the data stored in an addressed location; a plurality of address registers for storing row addresses of rows of the memory array of data stored in the data buffers; comparator means for comparing received addresses with addressses stored in the address registers to determine whether data to be addressed by a received row address is retained in a data buffer; and control means for causing a read from the memory array to a selected buffer when the row indicated by the received row address is not stored in a data buffer and for selecting a data buffer for direct access when the data is already stored in the buffer.

Claim 3

A memory as claimed in claim 1 wherein the memory array and data buffers are formed on a semiconductor chip.

Claim 4

A memory as claimed in claim 2 wherein the means for selecting one of the data buffers comprises at least one select terminal for receiving an input to the semiconductor chip.

Claim 5

A memory as claimed in claim 1 wherein the memory array and data buffers are formed on a memory chip, and the row address registers, the comparator means, and the control means are formed on a separate controller chip.

Claim 6

A memory as claimed in claim 1 wherein the address registers store virtual addresses corresponding to the row addresses of data stored in the data buffers and wherein the control means causes a read from the memory array to a selected buffer based on a physical address where the row being addressed is not stored in the data buffer and selects a buffer for direct access where the virtual address indicates that the data is already stored in the buffer.

Claim 7

A memory as claimed in claim 5 comprising separate virtual address registers and physical address registers, an initial comparison being made of a received virtual address to the addresses stored in the virtual address registers and a subsequent comparison being made of received physical addresses to the addresses stored in the physical address registers where the comparison of virtual addresses does not indicate that the data to be addressed is already stored in the data buffer.

Claim 8

A memory as claimed in claim 5 comprising plural banks of memory arrays, there being a single memory management unit associated with the plural banks of memory arrays to translate virtual addresses to physical addresses.

Claim 9

A memory as claimed in claim 7 comprising a separate virtual address register, comparator means and control means associated with each bank.

Claim 10

A memory as claimed in claim 1 further comprising means for storing data in the storage elements from the data buffer such that the memory is a random access memory.

Claim 11

A random access memory comprising: on a single semiconductor chip, a dynamic memory array logically arranged as rows and columns of storage elements addressable by row addresses, each row being directly accessible independent of other rows, and a plurality of static data buffers for storing data to be accessed by column addresses, each data buffer being connected to the memory array to receive and store a row of data from any addressed row of the array, to provide data as an output of the memory, to receive data as an input to the memory and to apply data to an addressed row of the array; means responsive to row addresses received by memory for directly addressing rows of the array for storage of rows in the data buffers; means for selecting one of the data buffers to receive and store data from addressed rows of the memory array; a plurality of address registers for storing row addresses of rows of the memory array of data stored in data buffers; comparator means for comparing received row addresses with addresses stored in the address registers to determine whether data to be addressed by a received row address is retained in a data buffer; and control means for causing a read from the memory array to a selected buffer when the row indicated by the received row address is not stored in a data buffer and for selecting a data buffer for direct access to the buffer with column addresses when the data is already stored in the buffer.

Claim 12

A random access memory comprising: on a single semiconductor chip, a dynamic memory array logically arranged as rows and columns of storage elements addressable by row addresses, each row being directly accessible independent of other rows, and a plurality of static data buffers for storing data to be accessed by column addresses, each data buffer being connected to the memory array to receive and store a row of data from any addressed row of the array, to provide data as an output of the memory, to receive data as an input to the memory and to apply data to an addressed row of the array; means responsive to row addresses received by memory for directly addressing rows of the array for storage of rows in the data buffers; means for selecting one of the data buffers to receive and store data from addressed rows of the memory array; a plurality of address registers for storing row addresses of rows of the memory array of data stored in data buffers; comparator means for comparing received row addresses with addresses stored in the address registers to determine whether data to be addressed by a received row address is retained in a data buffer; and control means for causing a read from the memory array to a selected buffer when the row indicated by the received row address is not stored in a data buffer and for selecting a data buffer for direct access to the buffer with column addresses when the data is already stored in the buffer.

Claim 13

A memory as claimed in claim 10 wherein the address registers store virtual addresses corresponding to the row addresses of data stored in the data buffers and wherein the control means causes a read from the memory array to a selected buffer and selects a buffer for direct access where the virtual address indicates that the data is already stored in the buffer.

Claim 14

A memory as claimed in claim 11 comprising separate virtual address registers and physical address registers, an initial comparison being made of a received virtual address to the addresses stored in the virtual address registers and a subsequent comparison being made of received physical addresses to the addresses stored in the physical address registers where the comparison of virtual addresses does not indicate that the data to be addressed is already stored in the data buffer.

Claim 15

A memory comprising, on a single semiconductor chip: a memory array logically arranged as rows and columns of storage elements addressible by row addresses, each row being directly accessible independent of other rows; means responsive to row addresses received by memory for directly addressing rows of the array for storage of rows in data buffers; a plurality of data buffers, each data buffer being connected to the memory array to receive and store a row of data from any addressed row of the array and to provide data as an output of the memory; means for selecting one of the data buffers to receive and store data from the memory array and to output data from the memory array; and means responsive to a column address for addressing bits of data from a selected data buffer.

Claim 16

A memory comprising, on a single semiconductor chip: a memory array logically arranged as rows and columns of storage elements addressible by row addresses, each row being directly accessible independent of other rows; means responsive to row addresses received by memory for directly addressing rows of the array for storage of rows in data buffers; a plurality of data buffers, each data buffer being connected to the memory array to receive and store a row of data from any addressed row of the array and to provide data as an output of the memory; means for selecting one of the data buffers to receive and store data from the memory array and to output data from the memory array; and means responsive to a column address for addressing bits of data from a selected data buffer.

Claim 17

A memory as claimed in claim 13 wherein the means for selecting one of the data buffers comprises at least one select terminal for receiving an input to the semiconductor chip.

Claim 18

A memory as claimed in claim 13 wherein the memory array and data buffers are formed on a memory chip which further comprises row address registers for storing the addresses of rows corresponding to the data in the data buffers.

Claim 19

A memory as claimed in claim 13 wherein the memory array is of dynamic charge elements and the data buffers are static buffers.

Claim 20

A memory as claimed in claim 13 further comprising means for storing data in the storage elements from the data buffer such that the memory is a random access memory.

Claim 21

A random access memory comprising: a dynamic memory array of dynamic charge elements logically arranged as rows and columns addressable by row addresses, each row of dynamic charge elements being directly accessible independent of other rows; means responsive to row addresses received by memory for addressing rows of the array for storage of rows in data buffers; a plurality of static data buffers for storing data to be accessed by column addresses each data buffer being connected to the memory array to receive and store a row of data from any addressed row of the array, to provide data as an output of the memory, to receive data as an input to the memory and to apply data to an addressed row of the array; means for selecting one of the data buffers to receive and store data from the memory array; and means responsive to a column address for addressing locations within a selected data buffer to access the data stored in an addressed location.

Claim 22

A random access memory comprising: a dynamic memory array of dynamic charge elements logically arranged as rows and columns addressable by row addresses, each row of dynamic charge elements being directly accessible independent of other rows; means responsive to row addresses received by memory for addressing rows of the array for storage of rows in data buffers; a plurality of static data buffers for storing data to be accessed by column addresses each data buffer being connected to the memory array to receive and store a row of data from any addressed row of the array, to provide data as an output of the memory, to receive data as an input to the memory and to apply data to an addressed row of the array; means for selecting one of the data buffers to receive and store data from the memory array; and means responsive to a column address for addressing locations within a selected data buffer to access the data stored in an addressed location.

Claim 23

A random access memory device comprising, on a single semiconductor chip: a plurality of dynamic charge elements, each capable of storing a single bit of data; a plurality of static buffers, each of which is capable of holding a plurality of data bits; means responsive to range addresses received by memory for directly addressing a range of said dynamic charge elements equal in number to the capacity of each static buffer, independently of others of said dynamic charge elements, for storage of data bits in said static buffers; means for selecting one of said static buffers; means for selectively loading or storing said data bits of said addressed range of dynamic charge elements to or from the selected static buffer; at least one data line; and means responsive to a charge element address for addressing locations within the selected static buffer, for reading data bits from said addressed locations to said data lines and for writing data bits to said addressed locations from said data lines.

Claim 24

A random access memory device comprising, on a single semiconductor chip: a plurality of dynamic charge elements, each capable of storing a single bit of data; a plurality of static buffers, each of which is capable of holding a plurality of data bits; means responsive to range addresses received by memory for directly addressing a range of said dynamic charge elements equal in number to the capacity of each static buffer, independently of others of said dynamic charge elements, for storage of data bits in said static buffers; means for selecting one of said static buffers; means for selectively loading or storing said data bits of said addressed range of dynamic charge elements to or from the selected static buffer; at least one data line; and means responsive to a charge element address for addressing locations within the selected static buffer, for reading data bits from said addressed locations to said data lines and for writing data bits to said addressed locations from said data lines.

Claim 25

A memory device as claimed in claim 19 wherein: the dynamic charge elements are logically arranged in rows and columns in at least one rectangular array; and the capacity of each static buffer corresponds to that of a single row in the dynamic charge array; said means for addressing a range of dynamic charge elements selects a single row from within the charge array.

Claim 26

A memory device as claimed in claim 20 wherein: the means for selecting one of the static buffers comprises one or more input terminals to the chip; and a single set of address terminals provides both the means for addressing a range of charge elements and the means for addressing locations within the selected static buffer.

Claim 27

A memory device as claimed in claim 19 wherein: the means for selecting one of the static buffers comprises one or more input terminals to the chip.

Claim 28

A memory device as claimed in claim 19 wherein: a single set of address terminals provides both the means for addressing a range of charge elements and the means for addressing locations within the selected static buffer.

Claim 29

A memory device as claimed in claim 19 further comprising: a plurality of address buffers equal in number to the number of static buffers, each capable of storing the address of one of said ranges of dynamic charge elements; means for recording in each of said address registers the range of charge elements contained in its corresponding buffer; and means for storing the contents of the selected static buffer into the range of charge elements specified by the contents of its corresponding address register.

Claim 30

A memory device as claimed in claim 24 wherein: the means for selecting one of the static buffers comprises one or more input terminals to the chip; and a single set of address terminals provides both the means for addressing a range of charge elements and the means for addressing locations within the selected static buffer.

Claim 31

A memory device as claimed in claim 25 further comprising: an input row address strobe signal which assumes one of two states to specify whether said single set of address terminals is to address said range of charge elements or said locations within the selected static buffer, a transition in one direction on said strobe input causing said addressed range of charge elements to be copied into said selected static buffer and a transition in the other direction on said strobe input causing the contents of said selected static buffer to be written into a range of charge elements.

Claim 32

A random access memory device comprising: a plurality a dynamic charge elements, each capable of storing a single bit of data; a plurality of static buffers, each of which is capable of holding a plurality of data bits; means responsive to range addresses received by memory for directly addressing a range of adjacent dynamic charge elements independently of others of said dynamic charge elements, for storing of data bits in said static buffers; means for selecting one of said static buffers; means for selectively loading or storing said data bits of said addressed range of dynamic charge elements to or from the selected static buffer; at least one data line; and means responsive to a charge element address for addressing locations within the selected static buffer, for reading data bits from said addressed locations to said data lines and for writing data bits to said addressed locations from said data lines.

Claim 33

A random access memory device comprising: a plurality a dynamic charge elements, each capable of storing a single bit of data; a plurality of static buffers, each of which is capable of holding a plurality of data bits; means responsive to range addresses received by memory for directly addressing a range of adjacent dynamic charge elements independently of others of said dynamic charge elements, for storing of data bits in said static buffers; means for selecting one of said static buffers; means for selectively loading or storing said data bits of said addressed range of dynamic charge elements to or from the selected static buffer; at least one data line; and means responsive to a charge element address for addressing locations within the selected static buffer, for reading data bits from said addressed locations to said data lines and for writing data bits to said addressed locations from said data lines.

Claim 34

A memory device as claimed in claim 27 wherein: the dynamic charge elements are logically arranged in rows and columns in at least one rectangular array; the capacity of each static buffer corresponds to that of a single row in the dynamic charge array; and said means for addressing a range of dynamic charge elements selects a single row from within the charge array.

Claim 35

A memory device as claimed in claim 27 wherein: the means for selecting one of the static buffers comprises one or more input terminals to the chip; and a single set of address terminals provides both the means for addressing a range of charge elements and the means for addressing locations within the selected static buffer.

Claim 36

A memory device as claimed in claim 27 wherein: the means for selecting one of the static buffers comprises one or more input terminals to the chip.

Claim 37

A memory device as claimed in claim 27 wherein: a single set of address terminals provides both the means for addressing a range of charge elements and the means for addressing locations within the selected static buffer.

Claim 38

A memory device as claimed in claim 27 further comprising: a plurality of address buffers equal in number to the number of static buffers, each capable of storing the address of one of said ranges of dynamic charge elements; means for recording in each of said address registers the range of charge elements contained in its corresponding buffer; and means for storing the contents of the selected static buffer into the range of charge elements specified by the contents of its corresponding address register.

Claim 39

A memory device as claimed in claim 27 wherein: the means for selecting one of the static buffers comprises one or more input terminals to the chip; and a single set of address terminals provides both the means for addressing a range of charge elements and the means for addressing locations within the selected static buffer.

Claim 40

A memory device as claimed in claim 27 further comprising: an input row address strobe signal which assumes one of two states to specify whether said single set of address terminals is to address said range of charge elements or said locations within the selected static buffer, a transition in one direction on said strobe input causing said addressed range of charge elements to be copied into said selected static buffer and a transition in the other direction of said strobe input causing the contents of said selected static buffer to be written into a range of charge elements.

Claim 41

A memory device comprising, on a single semiconductor chip: a plurality of memory elements, each capable of storing a single bit of data; a plurality of static buffers, each of which is capable of holding a plurality of data bits; means responsive to range addresses received by memory for directly addressing a range of memory elements, equal in number to the capacity of each static buffer, for storage of data bits in said static buffers; means for selecting one of said static buffers; means for selectively loading data from said addressed range of memory elements into a selected static buffer; at least one data line; and means responsive to a memory element address for addressing locations within the selected static buffer, and for reading data from said addressed locations onto said data lines.

Claim 42

A memory device comprising, on a single semiconductor chip: a plurality of memory elements, each capable of storing a single bit of data; a plurality of static buffers, each of which is capable of holding a plurality of data bits; means responsive to range addresses received by memory for directly addressing a range of memory elements, equal in number to the capacity of each static buffer, for storage of data bits in said static buffers; means for selecting one of said static buffers; means for selectively loading data from said addressed range of memory elements into a selected static buffer; at least one data line; and means responsive to a memory element address for addressing locations within the selected static buffer, and for reading data from said addressed locations onto said data lines.

Claim 43

A memory device comprising: a plurality of memory elements, each capable of storing a single bit of data; a plurality of static buffers, each of which is capable of holding a plurality of data bits; means responsive to range addresses received by memory for directly addressing a range of adjacent memory elements, for storage of data bits in said static buffers; means for selecting one of said static buffers; means for selectively loading data from said addressed range of elements into a selected static buffer; at least one data line; and means responsive to a memory element address for addressing locations within the selected static buffer, and for reading data from said addressed locations onto said data lines.

Claim 44

A memory device comprising: a plurality of memory elements, each capable of storing a single bit of data; a plurality of static buffers, each of which is capable of holding a plurality of data bits; means responsive to range addresses received by memory for directly addressing a range of adjacent memory elements, for storage of data bits in said static buffers; means for selecting one of said static buffers; means for selectively loading data from said addressed range of elements into a selected static buffer; at least one data line; and means responsive to a memory element address for addressing locations within the selected static buffer, and for reading data from said addressed locations onto said data lines.

Claim 45

A memory controller chip comprising: input lines for a memory address; a plurality of address registers for holding addresses from the input lines; a plurality of comparators, each of which compares an incoming address on the address lines with the contents of a corresponding one of the address registers; set select output signals for selecting one of a plurality of static buffers contained within an external bank of dynamic memory devices in response to the comparison of addresses; memory control output signals for signaling the reading and writing of the contents of the selected buffers from and to an external dynamic memory; logic which generates said control signals so as to access said static buffers directly if said comparators indicate a match with the incoming address; and logic which selects a buffer to be reloaded, generates said control signals so as to replace the previous contents of the selected buffer into the dynamic memory and read new contents containing the addressed location if said comparators do not indicate a match with the incoming address.

Claim 46

A memory controller chip comprising: input lines for a memory address; a plurality of address registers for holding addresses from the input lines; a plurality of comparators, each of which compares an incoming address on the address lines with the contents of a corresponding one of the address registers; set select output signals for selecting one of a plurality of static buffers contained within an external bank of dynamic memory devices in response to the comparison of addresses; memory control output signals for signaling the reading and writing of the contents of the selected buffers from and to an external dynamic memory; logic which generates said control signals so as to access said static buffers directly if said comparators indicate a match with the incoming address; and logic which selects a buffer to be reloaded, generates said control signals so as to replace the previous contents of the selected buffer into the dynamic memory and read new contents containing the addressed location if said comparators do not indicate a match with the incoming address.

Claim 47

A controller as claimed in claim 37 wherein the address registers and comparators include a plurality of virtual address registers and comparators and a plurality of physical address registers and comparators.

Claim 50

A method as claimed in claim 39 wherein virtual addresses are compared with addresses of data stored in the data buffers.

Claim 51

A method as claimed in claim 39 further comprising, where the row indicated by the received address is not stored in a data buffer, writing the contents of a selected data buffer into a row of the memory array prior to reading the row indicated by the received address from the array.