Semiconductor memory device for simple cache system

Claim 2

A semiconductor memory device containing a cache memory, comprising, on a single chip: a first memory cell array comprising a plurality of word lines, a plurality of bit line pairs perpendicular to said plurality of word lines and a plurality of memory cells arranged in a matrix of a plurality of rows corresponding to said word lines and columns corresponding to said bit line pairs, said first memory cell array being divided into a plurality of blocks each comprising a plurality of columns, a cache memory including a second memory cell array comprising a plurality of static type memory cells arranged in a plurality of rows and a plurality of columns corresponding to said plurality of columns in said first memory cell array, said second memory cell array being divided into a plurality of blocks each comprising a plurality of columns, each said static type memory cell being aligned with and connected to one of said plurality of bit line pairs, first access means responsive to a cache miss indicating signal for accessing data at a memory cell of said first memory cell array selected by a first row address signal and a column address signal, said first access means comprising block selecting means responsive to a block selecting signal for selecting any of said plurality of blocks in said first memory cell array, second access means responsive to a cache hit indicating signal for accessing data at a static type memory cell selected by a second row address signal and a column address signal, and data transfer means for transferring data between a column in said first memory cell array and a respective column in said second memory cell array.

Claim 3

The semiconductor memory device according to claim 1, which further comprises: switching means responsive to said cache miss indicating signal for activating said data transfer means.

Claim 4

The semiconductor memory device according to claim 1, wherein said block selecting signal comprises a part of a column address signal.

Claim 5

The semiconductor memory device according to claim 1, wherein said first access means comprises first row selecting means responsive to said first row address signal for selecting any of said plurality of rows in said first memory cell array, and column selecting means responsive to said column address signal for selecting any of said plurality of columns in said first memory cell array, and said second access means comprises second row selecting means responsive to said second row address signal for selecting any of plurality of rows in said second cache memory cell array.

Claim 6

The semiconductor memory device according to claim 4, which further comprises: data input/output means for inputting/outputting data to/from a memory cell selected by said first row selecting means and said column selecting means or a static type memory cell selected by said second row selecting means and said column selecting means.

Claim 7

The semiconductor memory device according to claim 4, which further comprises: a plurality of sense amplifiers for detecting and holding data on the row selected by said first row selecting means.

Claim 8

The semiconductor memory device according to claim 4, wherein said second row selecting means further comprises means for inactivating all the static type memory cells included in said second cache memory cell array.

Claim 9

The semiconductor memory device according to claim 1, wherein each of said plurality of memory cells included in said first memory cell array comprises a dynamic type memory cell.

Claim 10

A semiconductor memory device containing a cache memory as recited in claim 1, wherein said first access means is responsive to a row activating signal, said row activating signal being in an activated state during occurrence of said cache hit indicating signal.

Claim 11

The semiconductor device according to claim 1, wherein each of said blocks have a predetermined equal number of bit line pairs and each of said blocks of said cache memory include said predetermined equal number of columns.

Claim 12

The semiconductor device according to claim 10, wherein said first and second memory cell arrays are divided into equal numbers of blocks.

Claim 13

A semiconductor memory device containing a cache memory, comprising, on a single chip: a dynamic random access memory comprising a plurality of word lines, a plurality of bit line pairs arranged so as to intersect with said plurality of word lines and a plurality of memory cells at intersections of said plurality of word lines and said plurality of bit line pairs, and a cache memory comprising a plurality of stages of storage means groups, each storage means group having a plurality of storage means, each storage means being physically aligned with and connected to one of said plurality of bit line pairs.

Claim 14

A semiconductor memory device containing a cache memory, comprising, on a single chip: a dynamic random access memory comprising a plurality of word lines, a plurality of bit line pairs arranged so as to intersect with said plurality of word lines and a plurality of memory cells at intersections of said plurality of word lines and said plurality of bit line pairs, and a cache memory comprising a plurality of stages of storage means groups, each storage means group having a plurality of storage means, each storage means being physically aligned with and connected to one of said plurality of bit line pairs.

Claim 15

A semiconductor memory device containing a cache memory, comprising, on a single chip: a dynamic random access memory comprising a plurality of word lines, a plurality of bit line pairs arranged so as to intersect with said plurality of word lines and a plurality of memory cells at intersection of said plurality of word lines and said plurality of bit line pairs, a cache memory comprising a plurality of storage means arranged in rows and columns, each of said cache memory storage means being physically aligned with a respective bit line pair, and a plurality of transfer gates, one transfer gate for each column of said storage means of cache memory and connectable to one of said bit line pairs of dynamic random access memory.

Claim 16

A semiconductor memory device containing a cache memory, comprising, on a single chip: a dynamic random access memory comprising a plurality of word lines, a plurality of bit line pairs arranged so as to intersect with said plurality of word lines and a plurality of memory cells at intersection of said plurality of word lines and said plurality of bit line pairs, a cache memory comprising a plurality of storage means arranged in rows and columns, each of said cache memory storage means being physically aligned with a respective bit line pair, and a plurality of transfer gates, one transfer gate for each column of said storage means of cache memory and connectable to one of said bit line pairs of dynamic random access memory.

Claim 17

A semiconductor memory device containing a cache memory, comprising, on a single chip: a first memory cell array comprising a plurality of word lines, a plurality of bit line pairs perpendicular to said plurality of word lines and a plurality of memory cells arranged in a matrix of a plurality of rows corresponding to said word lines and columns corresponding to said bit line pairs, said first memory cell array being divided into a plurality of blocks each comprising a plurality of columns, a cache memory including a second memory cell array comprising a plurality of blocks, each block having a plurality of static type memory cells arranged in one or more rows and a plurality of columns corresponding to said plurality of columns included in each of said blocks of said first memory cell array, each said static type memory cells being aligned with one of said bit line pairs, first access means responsive to a cache miss indicating signal for accessing data at a memory cell of said first memory cell array selected by a first row address signal and a column address signal, said first access means comprising block selecting means responsive to a block selecting signal for selecting any of said plurality of blocks in said first memory cell array, second access means responsive to a cache hit indicating signal for accessing data at a static type memory cell selected by a second row address signal and a column address signal, and data transfer means for transferring data from memory cells in a row of block of said first memory cell array selected by said block selecting means to memory cells in a row of a selected block of said second memory cell array.

Claim 18

A semiconductor memory device containing a cache memory, comprising, on a single chip: a first memory cell array comprising a plurality of word lines, a plurality of bit line pairs perpendicular to said plurality of word lines and a plurality of memory cells arranged in a matrix of a plurality of rows corresponding to said word lines and columns corresponding to said bit line pairs, said first memory cell array being divided into a plurality of blocks each comprising a plurality of columns, a cache memory including a second memory cell array comprising a plurality of blocks, each block having a plurality of static type memory cells arranged in one or more rows and a plurality of columns corresponding to said plurality of columns included in each of said blocks of said first memory cell array, each said static type memory cells being aligned with one of said bit line pairs, first access means responsive to a cache miss indicating signal for accessing data at a memory cell of said first memory cell array selected by a first row address signal and a column address signal, said first access means comprising block selecting means responsive to a block selecting signal for selecting any of said plurality of blocks in said first memory cell array, second access means responsive to a cache hit indicating signal for accessing data at a static type memory cell selected by a second row address signal and a column address signal, and data transfer means for transferring data from memory cells in a row of block of said first memory cell array selected by said block selecting means to memory cells in a row of a selected block of said second memory cell array.

Claim 19

The semiconductor memory device according to claim 14, wherein each memory cell of said first memory cell array is a dynamic type memory cell.

Claim 20

The semiconductor memory device according to claim 14, wherein said static type memory cells of said blocks of said second memory cell array are arranged in at least two rows.

Claim 21

A semiconductor memory device containing a cache memory, comprising, on a single chip: a dynamic random access memory comprising a plurality of bit lines, a plurality of first blocks each having a plurality of dynamic type memory cells arranged in a matrix of a plurality of rows and a plurality of columns corresponding to said bit lines, a number of columns in each first block being equal, a cache memory comprising a plurality of second blocks each having a plurality of static type memory cells arranged in one or more rows and a plurality of columns, a number of columns in each of said second blocks being equal to the number of columns in said first blocks, each of said static type memory cells being aligned with one of said bit lines, and data transfer means for transferring data from dynamic type memory cells in a row of one of said first blocks of said dynamic random access memory to static type memory cells in a row of one of said second blocks of said cache memory.

Claim 22

A semiconductor memory device containing a cache memory, comprising, on a single chip: a dynamic random access memory comprising a plurality of bit lines, a plurality of first blocks each having a plurality of dynamic type memory cells arranged in a matrix of a plurality of rows and a plurality of columns corresponding to said bit lines, a number of columns in each first block being equal, a cache memory comprising a plurality of second blocks each having a plurality of static type memory cells arranged in one or more rows and a plurality of columns, a number of columns in each of said second blocks being equal to the number of columns in said first blocks, each of said static type memory cells being aligned with one of said bit lines, and data transfer means for transferring data from dynamic type memory cells in a row of one of said first blocks of said dynamic random access memory to static type memory cells in a row of one of said second blocks of said cache memory.

Claim 23

The semiconductor memory device according to claim 17, wherein said static type memory cells of said second blocks are arranged in at least two rows.

Claim 24

A semiconductor memory device containing a cache memory, comprising, on a single chip: a first memory cell array comprising a plurality of word lines, a plurality of bit line pairs of perpendicular to said plurality of word lines and a plurality of memory cells arranged in a matrix of a plurality of rows corresponding to said word lines and columns corresponding to said bit line pairs a cache memory including a second memory cell array comprising a plurality of static type memory cells arranged in a plurality of rows and a plurality of columns corresponding to said plurality of columns in said first memory cell array each said static type memory cell being aligned with and connected to one of said plurality of bit line pairs, first access means responsive to a cache miss indicating signal for accessing data at a memory cell of said first memory cell array selected by a first row address signal and a column address signal, second access means responsive to a cache hit indicating signal for accessing data at a static type memory cell selected by a second row address signal and a column address signal, and data transfer means for transferring data between a column in said first memory cell array and a respective column in said second memory cell array.

Claim 25

A semiconductor memory device containing a cache memory, comprising, on a single chip: a first memory cell array comprising a plurality of word lines, a plurality of bit line pairs of perpendicular to said plurality of word lines and a plurality of memory cells arranged in a matrix of a plurality of rows corresponding to said word lines and columns corresponding to said bit line pairs a cache memory including a second memory cell array comprising a plurality of static type memory cells arranged in a plurality of rows and a plurality of columns corresponding to said plurality of columns in said first memory cell array each said static type memory cell being aligned with and connected to one of said plurality of bit line pairs, first access means responsive to a cache miss indicating signal for accessing data at a memory cell of said first memory cell array selected by a first row address signal and a column address signal, second access means responsive to a cache hit indicating signal for accessing data at a static type memory cell selected by a second row address signal and a column address signal, and data transfer means for transferring data between a column in said first memory cell array and a respective column in said second memory cell array.