Nonvolatile multivalue memory

Claim 2

A nonvolatile multivalue memory comprising: a memory cell array having a plurality of word lines, a plurality of bit lines, and memory cells each arranged at an intersection between each word line and each bit line; a memory cell transistor having a floating gate for holding nonvolatile information, and a control gate, connected to the word line, for controlling writing, erasing, or reading of information held in the floating gate, said memory cell transistor constituting said memory cell; drive signal means for supplying a drive signal to the control gate of said memory cell transistor, the drive signal alternately and repeatedly having a first potential and a second potential different from the first potential, said drive signal means includes: a multivalue program level generator for generating a program signal having multivalue levels corresponding to program data to be stored in said memory cell transistor; and a word line drive pulse generator for generating a pulse as the drive signal, the pulse alternately and repeatedly having the first potential corresponding to one of the multivalue levels of the program signal generated by said multivalue program level generator and a second potential different from the first potential.

Claim 3

A memory according to claim 1, wherein said drive signal means is means for simultaneously supplying the drive signal to the control gates of said memory cell transistors.

Claim 4

A memory according to claim 1, wherein said drive signal means is means for sequentially supplying the drive signal to the control gates of said memory cell transistors.

Claim 5

A nonvolatile multivalue memory comprising: a memory cell array having a plurality of word lines, a plurality of bit lines, and memory cells each arranged at an intersection between each word line and each bit line; a memory cell transistor having a floating gate for holding nonvolatile information, and a control gate, connected to the word line, for controlling writing, erasing, or reading of information held in the floating gate, said memory cell transistor constituting said memory cell; drive signal means for supplying a drive signal to the control gate of said memory cell transistor, the drive signal alternately and repeatedly having one of a plurality of types of first potentials and a second potential different from the first potentials, said drive signal means includes: a multivalue program level generator for generating a program signal having multivalue levels corresponding to program data to be stored in said memory cell transistor; and a word line drive pulse generator for generating a pulse as the drive signal, the pulse alternately and repeatedly having the first potential corresponding to one of the multivalue levels of the program signal generated by said multivalue program level generator and a second potential different from the first potential.

Claim 6

A nonvolatile multivalue memory comprising: a memory cell array having a plurality of word lines, a plurality of bit lines, and memory cells each arranged at an intersection between each word line and each bit line; a memory cell transistor having a floating gate for holding nonvolatile information, and a control gate, connected to the word line, for controlling writing, erasing, or reading of information held in the floating gate, said memory cell transistor constituting said memory cell; drive signal means for supplying a drive signal to the control gate of said memory cell transistor, the drive signal alternately and repeatedly having one of a plurality of types of first potentials and a second potential different from the first potentials, said drive signal means includes: a multivalue program level generator for generating a program signal having multivalue levels corresponding to program data to be stored in said memory cell transistor; and a word line drive pulse generator for generating a pulse as the drive signal, the pulse alternately and repeatedly having the first potential corresponding to one of the multivalue levels of the program signal generated by said multivalue program level generator and a second potential different from the first potential.

Claim 7

A memory according to claim 4, wherein said drive signal means is means for simultaneously supplying the drive signal to the control gates of said memory cell transistors.

Claim 8

A memory according to claim 4, wherein said drive signal means is means for sequentially supplying the drive signal to the control gates of said memory cell transistors.

Claim 9

A nonvolatile multivalue memory comprising: a memory cell array having a plurality of word lines, a plurality of bit lines, and memory cells each arranged at an intersection between each word line and each bit line; a memory cell transistor having a floating gate for holding nonvolatile information, and a control gate, connected to the word line, for controlling writing, erasing, or reading of information held in the floating gate, said memory cell transistor having a source and drain one of which is coupled to said bit line and the other of which is coupled to a predetermined circuit with a predetermined potential and constituting said memory cell; drive signal means for supplying a drive signal to the control gate of said memory cell transistor, the drive signal alternately and repeatedly having a first potential and a second potential different from the first potential; and means for setting said bit line in a floating state higher in potential than the circuit predetermined potential before applying said drive signal to the control gate of said memory cell transistor.

Claim 10

A nonvolatile multivalue memory comprising: a memory cell array having a plurality of word lines, a plurality of bit lines, and memory cells each arranged at an intersection between each word line and each bit line; a memory cell transistor having a floating gate for holding nonvolatile information, and a control gate, connected to the word line, for controlling writing, erasing, or reading of information held in the floating gate, said memory cell transistor having a source and drain one of which is coupled to said bit line and the other of which is coupled to a predetermined circuit with a predetermined potential and constituting said memory cell; drive signal means for supplying a drive signal to the control gate of said memory cell transistor, the drive signal alternately and repeatedly having a first potential and a second potential different from the first potential; and means for setting said bit line in a floating state higher in potential than the circuit predetermined potential before applying said drive signal to the control gate of said memory cell transistor.

Claim 11

A memory according to claim 7, wherein said drive signal means includes: a multivalue program level generator for generating a program signal having multivalue levels corresponding to program data to be stored in said memory cell transistor; and a word line drive pulse generator for generating a pulse as the drive signal, the pulse alternately and repeatedly having the first potential corresponding to one of the multivalue levels of the program signal generated by said multivalue program level generator and a second potential different from the first potential.

Claim 12

A memory according to claim 7, wherein said drive signal means is means for simultaneously supplying the drive signal to the control gates of said memory cell transistors.

Claim 13

A memory according to claim 7, wherein said drive signal means is means for sequentially supplying the drive signal to the control gates of said memory cell transistors.

Claim 14

A memory according to claim 9, wherein said drive signal means includes: a multivalue program level generator for generating a program signal having multivalue levels corresponding to program data to be stored in said memory cell transistor; and a word line drive pulse generator for generating a pulse as the drive signal, the pulse alternately and repeatedly having the first potential corresponding to one of the multivalue levels of the program signal generated by said multivalue program level generator and a second potential different from the first potential.

Claim 15

A memory according to claim 10, wherein said drive signal means includes: a multivalue program level generator for generating a program signal having multivalue levels corresponding to program data to be stored in said memory cell transistor; and a word line drive pulse generator for generating a pulse as the drive signal, the pulse alternately and repeatedly having the first potential corresponding to one of the multivalue levels of the program signal generated by said multivalue program level generator and a second potential different from the first potential.

Claim 16

A nonvolatile multivalue memory comprising: a memory cell array having a plurality of word lines, a plurality of bit lines, and memory cells each arranged at an intersection between each word line and each bit line; a memory cell transistor having a floating gate for holding nonvolatile information, and a control gate, connected to the word line, for controlling writing, erasing, or reading of information held in the floating gate, said memory cell transistor having a source and drain one of which is coupled to said bit line and the other of which is coupled to a predetermined circuit with a predetermined potential and constituting said memory cell; drive signal means for supplying a drive signal to the control gate of said memory cell transistor, the drive signal alternately and repeatedly having one of a plurality of types of first potentials and a second potential different from the first potentials; and means for setting said bit line in a floating state higher in potential than the circuit predetermined potential before applying said drive signal to the control gate of said memory cell transistor.

Claim 17

A nonvolatile multivalue memory comprising: a memory cell array having a plurality of word lines, a plurality of bit lines, and memory cells each arranged at an intersection between each word line and each bit line; a memory cell transistor having a floating gate for holding nonvolatile information, and a control gate, connected to the word line, for controlling writing, erasing, or reading of information held in the floating gate, said memory cell transistor having a source and drain one of which is coupled to said bit line and the other of which is coupled to a predetermined circuit with a predetermined potential and constituting said memory cell; drive signal means for supplying a drive signal to the control gate of said memory cell transistor, the drive signal alternately and repeatedly having one of a plurality of types of first potentials and a second potential different from the first potentials; and means for setting said bit line in a floating state higher in potential than the circuit predetermined potential before applying said drive signal to the control gate of said memory cell transistor.

Claim 18

A memory according to claim 13, wherein said drive signal means includes: a multivalue program level generator for generating a program signal having multivalue levels corresponding to program data to be stored in said memory cell transistor; and a word line drive pulse generator for generating a pulse as the drive signal, the pulse alternately and repeatedly having the first potential corresponding to one of the multivalue levels of the program signal generated by said multivalue program level generator and a second potential different from the first potential.

Claim 19

A memory according to claim 13, wherein said drive signal means is means for simultaneously supplying the drive signal to the control gates of said memory cell transistors.

Claim 20

A memory according to claim 13, wherein said drive signal means is means for sequentially supplying the drive signal to the control gates of said memory cell transistors.

Claim 21

A memory according to claim 15, wherein said drive signal means includes: a multivalue program level generator for generating a program signal having multivalue levels corresponding to program data to be stored in said memory cell transistor; and a word line drive pulse generator for generating a pulse as the drive signal, the pulse alternately and repeatedly having the first potential corresponding to one of the multivalue levels of the program signal generated by said multivalue program level generator and a second potential different from the first potential.

Claim 22

A memory according to claim 16, wherein said drive signal means includes: a multivalue program level generator for generating a program signal having multivalue levels corresponding to program data to be stored in said memory cell transistor; and a word line drive pulse generator for generating a pulse as the drive signal, the pulse alternately and repeatedly having the first potential corresponding to one of the multivalue levels of the program signal generated by said multivalue program level generator and a second potential different from the first potential.

Claim 23

In a nonvolatile multivalue memory comprising: a memory cell array having a plurality of word lines, a plurality of bit lines, and memory cells each arranged at an intersection between each word line and each bit line; a memory cell transistor having a floating gate for holding nonvolatile information, and a control gate, connected to the word line, for controlling writing, erasing, or reading of information held in the floating gate, said memory cell transistor having a source and drain one of which is coupled to said bit line and the other of which is coupled to a predetermined circuit with a predetermined potential and constituting said memory cell, and drive signal means for supplying a drive signal to the control gate of said memory cell transistor, the drive signal alternately and repeatedly having a first potential and a second potential different from the first potential, a write/erase method applied to the nonvolatile multivalue memory, comprising the steps of: setting said bit line in a floating state higher in potential than the circuit predetermined potential before applying said drive signal to the control gate of said memory cell transistor, and causing different floating gate voltages of many memory cell transistors to converge to a predetermined voltage by applying the drive signal to the floating gate of each of said memory cell transistors.

Claim 24

In a nonvolatile multivalue memory comprising: a memory cell array having a plurality of word lines, a plurality of bit lines, and memory cells each arranged at an intersection between each word line and each bit line; a memory cell transistor having a floating gate for holding nonvolatile information, and a control gate, connected to the word line, for controlling writing, erasing, or reading of information held in the floating gate, said memory cell transistor having a source and drain one of which is coupled to said bit line and the other of which is coupled to a predetermined circuit with a predetermined potential and constituting said memory cell, and drive signal means for supplying a drive signal to the control gate of said memory cell transistor, the drive signal alternately and repeatedly having a first potential and a second potential different from the first potential, a write/erase method applied to the nonvolatile multivalue memory, comprising the steps of: setting said bit line in a floating state higher in potential than the circuit predetermined potential before applying said drive signal to the control gate of said memory cell transistor, and causing different floating gate voltages of many memory cell transistors to converge to a predetermined voltage by applying the drive signal to the floating gate of each of said memory cell transistors.

Claim 25

In a nonvolatile multivalue memory as in claim 19, wherein the step of applying the drive signal to the floating gate occurs after a step of precharging said bit line and the method further includes performing a write/erase operation with respect to said memory cell transistor.

Claim 26

In a nonvolatile multivalue memory as in claim 19 wherein applying the drive signal to the floating gate includes interrupting the application of the alternately and repeatedly signal and during the interruption applying a short voltage pulse to said bit line to reset said bit line to said higher potential.