US5406521A
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Semiconductor memory device and data erase method for it
Assignee: NEC Electronics Corp
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Filing: 1993-11-01
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Granted: 1995-04-11
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Expires: 2013-11-01
Abstract
Abstract A semiconductor memory device comprises a plurality of word lines (WL1, WL2), a plurality of bit lines (BL1, BL"), a plurality of memory cells (MC11, MC12) each includes a transistor (9) formed on a first semiconductor region (3) and having a floating gate (6), a control gate (8) connected to one of said word lines, a source region (5s) and a drain region (5d) connected to a first end of one of said bit lines, and further comprises a source line (SL) having a first capacitance thereof different from a second capacitance which is associated with said bit lines (BL1, BL2) and having a first end thereof connected to said source region, a first bias means (14) for charging said bit lins and said source line via said first semicondictor region to a high voltage level (Vcc) during a first time period and supplying a low voltage level (Vss) to said first semiconductor region during a second time period thereafter, wherein said low voltage level causes a voltage difference and a current between said source and drain region according to a difference between said first and second capacitance, by which current electrons are injected to said floating gate.
Inventors
- 👤 Hideki Hara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:11
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/24; G11C16/10; G11C16/14; G11C16/16; G11C16/08
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
247 words
A semiconductor memory device comprising; a) a plurality of word lines (WL1, WL2); b) a plurality of bit lines (BL1, BL"); and c) a plurality of memory cells (MC11, MC12) each includes a transistor (9) formed on a first semiconductor region (3) and having a floating gate (6), a control gate (8) connected to one of said word lines, a source region (5s) and a drain region (5d) connected to a first end of one of said bit lines, characteriyed by d) a source line (SL) having a first capacitance thereof different from a second capacitance which is associated with said bit lines (BL1, BL2) and having a first end thereof connected to said source region, e) a first bias means (14) for charging said bit lins and said source line via said first semicondictor region to a high voltage level (Vcc), f) a control means (18) for outputting a first and a second signal to said first bias means consecutively, wherein said first bias means is activated by said first signal to charge said bit lines and said source line in a first time period, said first bias means is switched to supply a low voltage level (Vss) to said first semiconductor region during a second time period, said source and drain region provide a voltage difference and a current therebetween according to said second signal owing to a difference between said first and second capacitance, by which current electrons are injected to said floating gate.
Claim 2
Dependent Claim
247 words
A semiconductor memory device comprising; a) a plurality of word lines (WL1, WL2); b) a plurality of bit lines (BL1, BL"); and c) a plurality of memory cells (MC11, MC12) each includes a transistor (9) formed on a first semiconductor region (3) and having a floating gate (6), a control gate (8) connected to one of said word lines, a source region (5s) and a drain region (5d) connected to a first end of one of said bit lines, characteriyed by d) a source line (SL) having a first capacitance thereof different from a second capacitance which is associated with said bit lines (BL1, BL2) and having a first end thereof connected to said source region, e) a first bias means (14) for charging said bit lins and said source line via said first semicondictor region to a high voltage level (Vcc), f) a control means (18) for outputting a first and a second signal to said first bias means consecutively, wherein said first bias means is activated by said first signal to charge said bit lines and said source line in a first time period, said first bias means is switched to supply a low voltage level (Vss) to said first semiconductor region during a second time period, said source and drain region provide a voltage difference and a current therebetween according to said second signal owing to a difference between said first and second capacitance, by which current electrons are injected to said floating gate.
Claim 3
Dependent Claim
73 words
The semiconductor memory device as claimed in claim 1, characterized by a) a first switching means (22) for connecting a second end of said source line to a first high impedance node (NS) during said first time period, and b) a second switching means (21) for connecting a second end of each of said bit lines (BL1, BL2) to a second high impedance node (ND1, ND2) corresponding thereto during said first time period.
Claim 4
Dependent Claim
56 words
The semiconductor memory device as claimed in claim 2, wherein said transistor stores data as a threshold voltage thereof which is determined by a voltage of said floating gate, characterized in that said voltage of said floating gate during said second time period determines an amount of said electrons which are injected to said floating gate.
Claim 5
Dependent Claim
52 words
The semiconductor memory device as claimed in claim 3, further comprising a word driver (11), characterized in that said control means (18) activates said word driver during said second time period, said word driver drives said control gate, by the level of which control gate said amount of said electrons is controled.
Claim 6
Dependent Claim
25 words
The semiconductor memory device as claimed in claim 4, characterized in that said control circuit outputs said first and second signal alternately in ceveral times.
Claim 7
Dependent Claim
216 words
A data erase method for a semiconductor memory device which comprises: a) a plurality of word lines (WL1, WL2); b) a plurality of bit lines (BL1, BL"); and c) a plurality of memory cells (MC11, MC12) each includes a transistor (9) formed on a first semiconductor region (3) and having a floating gate (6), a control gate (8) connected to one of said word lines, a source region (5s) and a drain region (5d) connected to a first end of one of said bit lines, characteriyed in that d) a source line (SL) is provided which has a first capacitance thereof different from a second capacitance associated with said bit lines (BL1, BL2), a first end of which source line is connected to said source region, e) a first bias means (14) charges said bit lins and said source line via said first semicondictor region to a high voltage level (Vcc) during a first time period, f) said first bias means supplies a low voltage level (Vss) to said first semiconductor region during a second time period following said first time period, which causes a voltage difference and a current between said source and drain region according to a difference between said first and second capacitance, by which current electrons are injected to said floating gate.
Claim 8
Dependent Claim
216 words
A data erase method for a semiconductor memory device which comprises: a) a plurality of word lines (WL1, WL2); b) a plurality of bit lines (BL1, BL"); and c) a plurality of memory cells (MC11, MC12) each includes a transistor (9) formed on a first semiconductor region (3) and having a floating gate (6), a control gate (8) connected to one of said word lines, a source region (5s) and a drain region (5d) connected to a first end of one of said bit lines, characteriyed in that d) a source line (SL) is provided which has a first capacitance thereof different from a second capacitance associated with said bit lines (BL1, BL2), a first end of which source line is connected to said source region, e) a first bias means (14) charges said bit lins and said source line via said first semicondictor region to a high voltage level (Vcc) during a first time period, f) said first bias means supplies a low voltage level (Vss) to said first semiconductor region during a second time period following said first time period, which causes a voltage difference and a current between said source and drain region according to a difference between said first and second capacitance, by which current electrons are injected to said floating gate.
Claim 9
Dependent Claim
72 words
The data erase method as claimed in claim 6, characterized in that a) a first switching means (22) connects a second end of said source line to a first high impedance node (NS) during said first time period, and b) a second switching means (21) connects a second end of each of said bit lines (BL1, BL2) to a second high impedance node (ND1, ND2) corresponding thereto during said first time period.
Claim 10
Dependent Claim
56 words
The data erase method as claimed in claim 7, wherein said transistor stores data as a threshold voltage thereof which is determined by a voltage of said floating gate, characterized in that said voltage of said floating gate during said second time period determines an amount of said electrons which are injected to said floating gate.
Claim 11
Dependent Claim
57 words
The data erase method as claimed in claim 8, wherein said semiconductor memory device further comprises a word driver (11), characterized in that a control means (18) activates said word driver during said second time period, said word driver drives said control gate, by the level of which control gate said amount of said electrons is controled.
Claim 12
Dependent Claim
55 words
The semiconductor memory device as claimed in claim 9, characterized in that said control circuit alternate activating said first bias means for charging said bit lines and said source line to said high voltage level with deactivating said first bias means for supplying said low voltage level to said first semiconductor region in several times.
References Cited (Backward Citations)
JPH01273296A
Cited
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