Patent EP0277279A2 successfully refreshed from Google Patents.
Patent US5600579A successfully refreshed from Google Patents.
US5600579A
Expired / Lapsed
US
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Hardware simulation and design verification system and method
Assignee: Apple Inc
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Filing: 1994-07-08
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Granted: 1997-02-04
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Expires: 2014-07-08
Abstract
Abstract A hardware design verification system has a hardware simulator, a test script, and a dispatcher, each preferably running as concurrent processes on a computer. The test script language is independent of the hardware simulator language. The hardware simulator simulates a hardware environment having a circuit under test coupled to a master model. To manipulate the hardware environment, the test script transmits a first packet to the dispatcher, the first packet being encoded in accordance with a predetermined encryption technique and designating a desired manipulation of the simulated hardware environment. The dispatcher, in response to receipt of the first packet, transmits the first packet to the master model, which in response decodes the first packet in accordance with the predetermined encryption technique and manipulates the hardware environment in accordance with the desired manipulation. In a preferred embodiment, the hardware simulator, dispatcher, and test script each rely on operating system facilities for packet transmission. For example, where the operating system is the UNIX system, one UNIX socket is dedicated for packet transmission between the test script and the dispatcher, and a second UNIX socket is dedicated to packet transmission between the hardware simulator and the dispatcher. When a desired hardware environment manipulation includes detecting the value of a signal in the circuit under test, the master model uses the predetermined encryption technique to encode the detected value into a packet. The packet is transmitted to the dispatcher, which forwards the packet to the test script.
Inventors
- 👤 William C. Steinmetz, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 01:03
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/3193
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
169 words
A hardware design verification system comprising: simulator means for simulating a hardware environment having a circuit under test coupled to a master model; test script means for executing a test script; dispatch means; first inter-task communication means for transmitting a packet from the test script means to the dispatch means: and second inter-task communication means for transmitting a packet from the dispatch means to the simulator means, wherein: the test script means uses the first inter-task communication means to transmit a first packet to the dispatch means, the first packet being encoded in accordance with a predetermined encryption technique and designating a desired manipulation of the simulated hardware environment; the dispatch means, in response to receipt of the first packet, uses the second inter-task communication means to transmit the first packet to the master model; and the master model, in response to receipt of the first packet, decodes the first packet in accordance with the predetermined encryption technique and manipulates the hardware environment in accordance with the desired manipulation.
Claim 2
Dependent Claim
169 words
A hardware design verification system comprising: simulator means for simulating a hardware environment having a circuit under test coupled to a master model; test script means for executing a test script; dispatch means; first inter-task communication means for transmitting a packet from the test script means to the dispatch means: and second inter-task communication means for transmitting a packet from the dispatch means to the simulator means, wherein: the test script means uses the first inter-task communication means to transmit a first packet to the dispatch means, the first packet being encoded in accordance with a predetermined encryption technique and designating a desired manipulation of the simulated hardware environment; the dispatch means, in response to receipt of the first packet, uses the second inter-task communication means to transmit the first packet to the master model; and the master model, in response to receipt of the first packet, decodes the first packet in accordance with the predetermined encryption technique and manipulates the hardware environment in accordance with the desired manipulation.
Claim 3
Dependent Claim
36 words
The system of claim 1, wherein each of the simulator means, test script means, and dispatch means is an executing computer program under control of an operating system that provides for concurrent execution of computer programs.
Claim 4
Dependent Claim
35 words
The system of claim 2, wherein: the operating system is a UNIX operating system; the first inter-task communication means is a first UNIX socket; and the second inter-task communication means is a second UNIX socket.
Claim 5
Dependent Claim
25 words
The system of claim 3, wherein each of the simulator means and test script means is a process that is forked from the dispatch means.
Claim 6
Dependent Claim
19 words
The system of claim 1, wherein the predetermined encryption technique includes converting an integer value into a character string.
Claim 7
Dependent Claim
149 words
The system of claim 1, wherein: the first inter-task communication means is further for transmitting a packet from the dispatch means to the test script means; the second inter-task communication means is further for transmitting a packet from the simulator means to the dispatch means; the desired manipulation includes detecting a signal value in the circuit under test; and the master model, after detecting the signal value, uses the predetermined encryption technique to include the detected signal value in a second packet and uses the second inter-task communication means to transmit the second packet to the dispatch means; the dispatch means, in response to receipt of the second packet, uses the first inter-task communication means to transmit the second packet to the test script means; and the test script means, in response to receipt of the second packet, decodes the second packet in accordance with the predetermined encryption technique.
Claim 8
Dependent Claim
89 words
The system of claim 1, wherein: each of the first and second inter-task communication means includes means for inputting a designation of one of a plurality of concurrent transmission streams with which a transmitted packet is to be associated; and in response to receiving, from the first inter-task communication means, a packet associated with a first transmission stream, the dispatch means designates a corresponding one of the plurality of concurrent transmission streams when it uses the second inter-task communication means to transmit the received packet to the master model.
Claim 9
Independent Claim
149 words
A method of verifying a hardware design of a circuit under test, comprising the steps of: in a computer, concurrently running a hardware simulator, a dispatcher, and a test script, wherein the hardware simulator simulates a hardware environment having the circuit under test coupled to a master model; using first means for inter-task communication to transmit, from the test script to the dispatcher, a first packet that is encoded in accordance with a predetermined encryption technique, wherein contents of the first packet designate a desired manipulation of the simulated hardware environment; using second means for inter-task communication to transmit the first packet from the dispatcher to the hardware simulator; in the hardware simulator, receiving the first packet and, in response thereto, using the master model to decode the first packet in accordance with the predetermined encryption technique and to manipulate the hardware environment in accordance with the desired manipulation.
Claim 10
Independent Claim
149 words
A method of verifying a hardware design of a circuit under test, comprising the steps of: in a computer, concurrently running a hardware simulator, a dispatcher, and a test script, wherein the hardware simulator simulates a hardware environment having the circuit under test coupled to a master model; using first means for inter-task communication to transmit, from the test script to the dispatcher, a first packet that is encoded in accordance with a predetermined encryption technique, wherein contents of the first packet designate a desired manipulation of the simulated hardware environment; using second means for inter-task communication to transmit the first packet from the dispatcher to the hardware simulator; in the hardware simulator, receiving the first packet and, in response thereto, using the master model to decode the first packet in accordance with the predetermined encryption technique and to manipulate the hardware environment in accordance with the desired manipulation.
Claim 11
Dependent Claim
80 words
The method of claim 8, wherein: concurrent running of the hardware simulator, dispatcher, and test script is controlled by a UNIX operating system; the step of using the first means for inter-task communication to transmit the first packet from the test script to the dispatcher includes using a first UNIX socket; and the step of using the second means for inter-task communication to transmit the first packet from the dispatcher to the hardware simulator includes using a second UNIX socket.
Claim 12
Dependent Claim
54 words
The method of claim 9, wherein the step of concurrently running the hardware simulator, the dispatcher, and the test script comprises the steps of: running the dispatcher; forking off the hardware simulator as a first child process of the dispatcher; and forking off the test script as a second child process of the dispatcher.
Claim 13
Dependent Claim
19 words
The method of claim 8, wherein the predetermined encryption technique includes convening an integer value into a character string.
Claim 14
Dependent Claim
107 words
The method of claim 8, wherein: the desired manipulation includes detecting a signal value in the circuit under test, and further comprising the steps of: in the hardware simulator, using the master model to detect the signal value; in the hardware simulator, using the predetermined encryption technique to include the detected signal value in a second packet; transmitting the second packet from the hardware simulator to the second inter-task communication means in the dispatcher; transmitting the second packet from the first inter-task communication means in the dispatcher to the test script; and in the test script, decoding the second packet in accordance with the predetermined encryption technique.
Claim 15
Dependent Claim
122 words
The method of claim 8, wherein the step of using the second means for inter-task communication to transmit the first packet from the dispatcher to the hardware simulator comprises the steps of: in the dispatcher, using the second means for inter-task communication to receive the first packet and a designation that the first packet is associated with a first one of a plurality of concurrent first transmission streams; and in the dispatcher, supplying second means for inter-task communication with the received packet and a designation of a selected one of a plurality of concurrent second transmission streams, wherein the selected one of the plurality of concurrent second transmission streams corresponds to the first one of the plurality of concurrent first transmission streams.
Claim 16
Dependent Claim
170 words
The method of claim 8, further comprising the preliminary steps of: using a first programming language to generate a test script computer program comprising invocations of at least one of a plurality of predefined verification system functions; using a second programming language to generate a master model computer program comprising invocations of at least one of the plurality of predefined verification system functions; compiling the test script computer program to produce the test script, wherein the step of compiling the test script computer program includes accessing a shared library of functions to retrieve object code corresponding to the at least one of the plurality of predefined verification system functions invoked by the test script computer program; and compiling the master model computer program to produce the master model, wherein the step of compiling the master model computer program includes accessing the shared library of functions to retrieve object code corresponding to the at least one of the plurality of predefined verification system functions invoked by the master model computer program.
Claim 17
Dependent Claim
19 words
The method of claim 14, wherein the first programming language is not the same as the second programming language.
Claim 18
Dependent Claim
57 words
The method of claim 15, wherein: the at least one of the plurality of predefined verification system functions invoked by the test script computer program includes a first verification system function; and the at least one of the plurality of predefined verification system functions invoked by the master model computer program includes the first verification system function.
Claim 19
Dependent Claim
170 words
The method of claim 8, further comprising the preliminary steps of: using a first programming language to generate a test script computer program comprising invocations of at least one of a plurality of predefined verification system functions; using a second programming language to generate a master model computer program comprising invocations of at least one of the plurality of predefined verification system functions; compiling the test script computer program to produce the test script, wherein the step of compiling the test script computer program includes accessing a shared library of functions to retrieve object code corresponding to the at least one of the plurality of predefined verification system functions invoked by the test script computer program; and compiling a hardware simulator computer program to produce the hardware simulator, wherein the step of compiling the hardware simulator computer program includes accessing the shared library of functions to retrieve object code corresponding to the at least one of the plurality of predefined verification system functions invoked by the master model computer program.
Claim 20
Dependent Claim
19 words
The method of claim 17, wherein the first programming language is not the same as the second programming language.
Claim 21
Dependent Claim
57 words
The method of claim 18, wherein: the at least one of the plurality of predefined verification system functions invoked by the test script computer program includes a first verification system function; and the at least one of the plurality of predefined verification system functions invoked by the master model computer program includes the first verification system function.
Claim 22
Independent Claim
350 words
A method for making test script means and a master model, each for use in a hardware design verification system comprising: simulator means for simulating a hardware environment having a circuit under test coupled to the master model; the test script means for executing a test script; dispatch means; first inter-task communication means for transmitting a packet from the test script means to the dispatch means; and second inter-task communication means for transmitting a packet from the dispatch means to the simulator means, wherein: the test script means uses the first inter-task communication means to transmit a first packet to the dispatch means, the first packet being encoded in accordance with a predetermined encryption technique and designating a desired manipulation of the simulated hardware environment; the dispatch means, in response to receipt of the first packet, uses the second inter-task communication means to transmit the first packet to the master model; and the master model, in response to receipt of the first packet, decodes the first packet in accordance with the predetermined encryption technique and manipulates the hardware environment in accordance with the desired manipulation, the method comprising the steps of: using a first programming language to generate a test script computer program comprising invocations of at least one of a plurality of predefined verification system functions; using a second programming language to generate a master model computer program comprising invocations of at least one of the plurality of predefined verification system functions; compiling the test script computer program to produce the test script, wherein the step of compiling the test script computer program includes accessing a shared library of functions to retrieve object code corresponding to the at least one of the plurality of predefined verification system functions invoked by the test script computer program; and compiling the master model computer program to produce the master model, wherein the step of compiling the master model computer program includes accessing the shared library of functions to retrieve object code corresponding to the at least one of the plurality of predefined verification system functions invoked by the master model computer program.
Claim 23
Independent Claim
350 words
A method for making test script means and a master model, each for use in a hardware design verification system comprising: simulator means for simulating a hardware environment having a circuit under test coupled to the master model; the test script means for executing a test script; dispatch means; first inter-task communication means for transmitting a packet from the test script means to the dispatch means; and second inter-task communication means for transmitting a packet from the dispatch means to the simulator means, wherein: the test script means uses the first inter-task communication means to transmit a first packet to the dispatch means, the first packet being encoded in accordance with a predetermined encryption technique and designating a desired manipulation of the simulated hardware environment; the dispatch means, in response to receipt of the first packet, uses the second inter-task communication means to transmit the first packet to the master model; and the master model, in response to receipt of the first packet, decodes the first packet in accordance with the predetermined encryption technique and manipulates the hardware environment in accordance with the desired manipulation, the method comprising the steps of: using a first programming language to generate a test script computer program comprising invocations of at least one of a plurality of predefined verification system functions; using a second programming language to generate a master model computer program comprising invocations of at least one of the plurality of predefined verification system functions; compiling the test script computer program to produce the test script, wherein the step of compiling the test script computer program includes accessing a shared library of functions to retrieve object code corresponding to the at least one of the plurality of predefined verification system functions invoked by the test script computer program; and compiling the master model computer program to produce the master model, wherein the step of compiling the master model computer program includes accessing the shared library of functions to retrieve object code corresponding to the at least one of the plurality of predefined verification system functions invoked by the master model computer program.
Claim 24
Dependent Claim
19 words
The method of claim 20, wherein the first programming language is not the same as the second programming language.
Claim 25
Dependent Claim
57 words
The method of claim 21, wherein: the at least one of the plurality of predefined verification system functions invoked by the test program computer program includes a first verification system function; and the at least one of the plurality of predefined verification system functions invoked by the master model computer program includes the first verification system function.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2000-02-04 | 2000-08-05 | 2001-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-04 | 2004-08-05 | 2005-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-04 | 2008-08-05 | 2009-02-04 | $7700.00 | Window Closed / Lapsed |