Digital circuit design assist system for designing hardware units and software units in a desired digital circuit, and method thereof

Claim 2

A digital circuit design assist system for designing a desired digital circuit consisting of a plurality of hardware units and at least one firmware unit for controlling said digital circuit as a unit, said system comprising: a functional model storage unit for storing each functional model functionally expressing each of said hardware units by a hardware description language through a text editor by coding input; a logic synthesis means for converting said functional model into a structural model structurally expressed by said hardware description language; a structural model storage unit for storing said structural model; a language model library storage unit for storing a language model expressing each of a plurality of components constituting each of said hardware units by said hardware description language; and a hardware description language simulation means for verifying whether or not the logic of each said hardware unit is correct with regard to said functional model, said structural model and said language model, via a test model which supplies a test pattern to each of said functional models and each of said structural models, and receives outputs from the models to verify the behaviors of the models.

Claim 3

A digital circuit design assist system according to claim 1, further comprising: a software program code interface for loading software, comprising said at least one firmware unit, an application program loaded to a storage unit of said digital circuit for executing a predetermined processes, and a diagnosis program for at least partially verifying the logic of said digital circuit, to said hardware description language simulation means, wherein said hardware description language simulation means further verifies whether software in a software unit in said digital circuit operates hardware units in said digital circuit as desired or not, and wherein memory such as RAM or ROM described in HDL is assigned in the digital circuit, software created as desired and stored in a storage in the digital circuit assist system by an assembler or a compiler is loaded to the memory by read/write statements of the hardware description language, a CPU provided in the digital circuit fetches the software for execution, and the software is verified by checking data written in the memory as a result of the execution of the software.

Claim 4

A digital circuit design assist system comprising a plurality of digital circuit design assist systems according to claim 2, wherein said hardware description language simulation means in each of said digital circuit design assist systems independently verifies each of said hardware units and each of said software units of said digital circuit from said functional model, said structural model, said language model and said software.

Claim 5

A digital circuit design assist system according to claim 3, further comprising: an automatic placing and routing tool for automatically carrying out layout for arranging said structural model in a physical space in said digital circuit, for example, on a printed board or on an integrated circuit, on the basis of the dimensions of components expressed by said structural model and the amount of wiring, when said structural models are input thereto.

Claim 6

A digital circuit design assist system according to claim 3, further comprising a fault analysis tool for analyzing a fault of said structural model.

Claim 7

A digital circuit design assist system according to claim 5, wherein said fault analysis tool includes an automatic test pattern generation tool for automatically generating a test pattern for analyzing a fault of said structural model.

Claim 8

A digital circuit design assist system according to claim 3, further comprising: a physical characteristics analysis tool for verifying whether or not said layout for arranging said structural models in a physical space in said digital circuit, for example, on a printed board or in an integrated circuit is appropriate, on the basis of physical characteristics such as wiring lines, delay times, exothermy, etc., of said structural model and/or radio waves, when said structural models are input thereto, and for evaluating the reliability of said digital circuit as an actual device when said layout is physically and actually realized.

Claim 9

A digital circuit design assist system according to claim 3, which further comprises at least one: a coding generation means for generating said structural model through a text editor by coding input; and a graphic generation means for generating said structural model through a block editor for expressing each of a plurality of components constituting each said hardware unit by an inherent symbol, drawing and arranging said symbols on a screen, drawing wiring between said arranged components, and processing therefor.

Claim 10

A digital circuit design assist system according to claim 8, wherein said hardware description language simulation means verifies the logic of said digital circuit comprising only said functional models, said functional models and said structural models or only said structural models, as one digital circuit.

Claim 11

A digital circuit design assist system according to any of claims 1 through 9, wherein said hardware description language is a VHDL.

Claim 12

A digital circuit design assist method using a plurality of digital circuit design assist systems for designing a desired digital circuit consisting of a plurality of hardware units and at least one firmware unit for controlling said digital circuit as a unit, said method comprising: a first step of generating each of functional models from each of a plurality of previously divided circuit units; a second step of verifying the logic of said hardware units in said digital circuit as a complete device by hardware description language simulation means from functional models and from language models individually expressing a plurality of components constituting each of said hardware units by a hardware description language, (i) at a functional level stage where only said functional models functionally express said digital circuit in said hardware description language; a third step of generating each of structural models having the same logic as that of the corresponding functional models by using any one of logic synthesis means for converting said functional models to said structural models structurally expressed by said hardware description language, coding generation means for generating new structural models through a text editor by coding input, and graphic generation means for generating new structural models through a block editor for expressing each of said components by an inherent symbol, drawing and arranging said symbols on a screen, drawing wires between said components arranged and image-processing them; a fourth step of executing verification of the logic of each of said divided hardware units in said digital circuit as a complete device by said hardware description language simulation means from said functional models, said structural models and language models, (ii) at the stage of a mixed level at which said digital circuit is expressed as a mixed state of said functional models and said structural models; and a fifth step of verifying the logic of said hardware units in said digital circuit as a complete device by said hardware description language simulation means from said structural models and said language models, (iii) at the stage of the structural level at which said digital circuit is expressed by only said structural models.

Claim 13

A digital circuit design assist method using a plurality of digital circuit design assist systems for designing a desired digital circuit consisting of a plurality of hardware units and at least one firmware unit for controlling said digital circuit as a unit, said method comprising: a first step of generating each of functional models from each of a plurality of previously divided circuit units; a second step of verifying the logic of said hardware units in said digital circuit as a complete device by hardware description language simulation means from functional models and from language models individually expressing a plurality of components constituting each of said hardware units by a hardware description language, (i) at a functional level stage where only said functional models functionally express said digital circuit in said hardware description language; a third step of generating each of structural models having the same logic as that of the corresponding functional models by using any one of logic synthesis means for converting said functional models to said structural models structurally expressed by said hardware description language, coding generation means for generating new structural models through a text editor by coding input, and graphic generation means for generating new structural models through a block editor for expressing each of said components by an inherent symbol, drawing and arranging said symbols on a screen, drawing wires between said components arranged and image-processing them; a fourth step of executing verification of the logic of each of said divided hardware units in said digital circuit as a complete device by said hardware description language simulation means from said functional models, said structural models and language models, (ii) at the stage of a mixed level at which said digital circuit is expressed as a mixed state of said functional models and said structural models; and a fifth step of verifying the logic of said hardware units in said digital circuit as a complete device by said hardware description language simulation means from said structural models and said language models, (iii) at the stage of the structural level at which said digital circuit is expressed by only said structural models.

Claim 14

A digital circuit design assist method using a plurality of digital circuit design assist systems for designing a desired digital circuit consisting of a plurality of hardware units and at least one firmware units for controlling said digital circuit as a unit, said method comprising: a first step of down-loading software comprising at least one of said firmware, an application program loaded in a storage unit of said digital circuit, for executing a predetermined processing, and a diagnostic program for verifying the logic at least a part of said digital circuit, to said hardware description language simulation means through a software program code interface; a second step of verifying the logic of said hardware units in said digital circuit as one complete digital circuit by said hardware description language simulation means from said functional models, a language models expressing individually a plurality of components constituting each of said hardware units by said hardware description language and said software, and verifying the logic of said software independently from the verification of the logic of said hardware units, (i) at the stage of the functional level at which said digital circuit is expressed by only said functional models functionally expressing each of said divided digital circuits by said hardware description language; a third step of generating said structural models by the use of at least one logic synthesis means for converting said functional models to said structural models structurally expressed by said hardware description language, coding generation means for generating new structural models through a text editor by coding input and graphic generation means for generating new structural models through a block editor for expressing each of said components by an inherent symbol, drawing and arranging said symbols on a screen, drawing wiring between said components and image-processing them; a fourth step of verifying the logic of said hardware units in said digital circuit as one complete digital circuit by said hardware description language simulation means from said functional models, said structural models, said language models and said software, and verifying the logic of said software independently from the verification of the logic of said hardware unit, (ii) at the stage of a mixed level where said digital circuit is expressed by said functional models and said structural models in a mixed state; and a fifth step of verifying the logic of said hardware units in said circuit as one complete digital circuit by said hardware description language simulation means from said structural models, said language models and said software, and verifying the logic from said software independently from the verification of the logic of said hardware units, (iii) at the stage of a structural level where said digital circuit is expressed by only said structural models.

Claim 15

A digital circuit design assist method using a plurality of digital circuit design assist systems for designing a desired digital circuit consisting of a plurality of hardware units and at least one firmware units for controlling said digital circuit as a unit, said method comprising: a first step of down-loading software comprising at least one of said firmware, an application program loaded in a storage unit of said digital circuit, for executing a predetermined processing, and a diagnostic program for verifying the logic at least a part of said digital circuit, to said hardware description language simulation means through a software program code interface; a second step of verifying the logic of said hardware units in said digital circuit as one complete digital circuit by said hardware description language simulation means from said functional models, a language models expressing individually a plurality of components constituting each of said hardware units by said hardware description language and said software, and verifying the logic of said software independently from the verification of the logic of said hardware units, (i) at the stage of the functional level at which said digital circuit is expressed by only said functional models functionally expressing each of said divided digital circuits by said hardware description language; a third step of generating said structural models by the use of at least one logic synthesis means for converting said functional models to said structural models structurally expressed by said hardware description language, coding generation means for generating new structural models through a text editor by coding input and graphic generation means for generating new structural models through a block editor for expressing each of said components by an inherent symbol, drawing and arranging said symbols on a screen, drawing wiring between said components and image-processing them; a fourth step of verifying the logic of said hardware units in said digital circuit as one complete digital circuit by said hardware description language simulation means from said functional models, said structural models, said language models and said software, and verifying the logic of said software independently from the verification of the logic of said hardware unit, (ii) at the stage of a mixed level where said digital circuit is expressed by said functional models and said structural models in a mixed state; and a fifth step of verifying the logic of said hardware units in said circuit as one complete digital circuit by said hardware description language simulation means from said structural models, said language models and said software, and verifying the logic from said software independently from the verification of the logic of said hardware units, (iii) at the stage of a structural level where said digital circuit is expressed by only said structural models.

Claim 16

A digital circuit design assist method using a plurality of digital circuit design assist systems for designing a desired digital circuit consisting of a plurality of hardware units and at least one firmware unit for controlling said digital circuit as a unit, said method comprising: a first step of creating a functional model functionally expressing a plurality of said divided digital circuits by a hardware description language; a second step of verifying the logic of said functional models by hardware description language simulation means and simultaneously executing substitution of said functional models to corresponding structural models without waiting for the verification of said logic, until creation of said functional models are completed; and a third step of independently executing automatic generation of layout for arranging said structural models in a physical space in said digital circuit, for example, on a printed board or on an integrated circuit by an automatic placing and routing tool on the basis of the dimensions of components expressed by said structural model and the amount of wiring, and verification of the logic of said hardware units.

Claim 17

A digital circuit design assist method using a plurality of digital circuit design assist systems for designing a desired digital circuit consisting of a plurality of hardware units and at least one firmware unit for controlling said digital circuit as a unit, said method comprising: a first step of creating a functional model functionally expressing a plurality of said divided digital circuits by a hardware description language; a second step of verifying the logic of said functional models by hardware description language simulation means and simultaneously executing substitution of said functional models to corresponding structural models without waiting for the verification of said logic, until creation of said functional models are completed; and a third step of independently executing automatic generation of layout for arranging said structural models in a physical space in said digital circuit, for example, on a printed board or on an integrated circuit by an automatic placing and routing tool on the basis of the dimensions of components expressed by said structural model and the amount of wiring, and verification of the logic of said hardware units.

Claim 18

A digital circuit design assist method according to claim 13, wherein said third step independently executes automatic generation of a test pattern for fault analysis of said structural models, analysis of any fault of said structural models and verification of the logic of said hardware units by an automatic test pattern tool and a fault analysis tool; on the basis of said digital circuit for which verification of said logic is under way or is completed, and wherein all of said functional models have already been converted to said structural models.

Claim 19

A digital circuit design assist method according to claim 13, wherein verification whether or not said layout arranging said structural models in a physical space in said digital circuit, for example, on a printed board or on an integrated circuit is appropriate, verification of reliability evaluation of an actual device of said digital circuit when mounted physically and actually, and verification of the logic of said hardware units, are executed independently by a physical characteristics analysis tool on the basis of physical characteristics such as the wiring lines, delay times, exothermy, etc., in said structural model and/or radio waves.

Claim 20

A digital circuit design assist system for designing a desired digital circuit consisting of a plurality of hardware units for controlling said digital circuit as a unit, said system comprising: a functional model storage unit for storing each functional model functionally expressing each of said hardware units by a hardware description language through a text editor by coding input; a logic synthesis means for converting said functional model into a structural model structurally expressed by said hardware description language; a structural model storage unit for storing said structural model; a language model library storage unit for storing a language model expressing each of a plurality of components constituting each of said hardware units by said hardware description language; and a hardware description language simulation means for verifying whether or not the logic of each said hardware unit is correct with regard to said functional model, said structural model and said language model, via a test model which supplies a test pattern to each of said functional models and each of said structural models and receives outputs from the models to verify the behaviors of the models.

Claim 21

A digital circuit design assist system for designing a desired digital circuit consisting of a plurality of hardware units for controlling said digital circuit as a unit, said system comprising: a functional model storage unit for storing each functional model functionally expressing each of said hardware units by a hardware description language through a text editor by coding input; a logic synthesis means for converting said functional model into a structural model structurally expressed by said hardware description language; a structural model storage unit for storing said structural model; a language model library storage unit for storing a language model expressing each of a plurality of components constituting each of said hardware units by said hardware description language; and a hardware description language simulation means for verifying whether or not the logic of each said hardware unit is correct with regard to said functional model, said structural model and said language model, via a test model which supplies a test pattern to each of said functional models and each of said structural models and receives outputs from the models to verify the behaviors of the models.

Claim 22

A digital circuit design assist method using a plurality of digital circuit design assist systems for designing a desired digital circuit consisting of a plurality of hardware units for controlling said digital circuit as a unit, said method comprising: a first step of generating each of functional models from each of a plurality of previously divided circuit units; a second step of verifying the logic of said hardware units in said digital circuit as a complete device by hardware description language simulation means from functional models and from language models individually expressing a plurality of components constituting each of said hardware units by a hardware description language, (i) at a functional level stage where only said functional models functionally express said digital circuit in said hardware description language; a third step of generating each of structural models having the same logic as that of the corresponding functional models by using any one of logic synthesis means for converting said functional models to said structural models structurally expressed by said hardware description language, coding generation means for generating new structural models through a text editor by coding input, and graphic generation means for generating new structural models through a block editor for expressing each of said components by an inherent symbol, drawing and arranging said symbols on a screen, drawing wires between said components arranged and image-processing them; a fourth step of executing verification of the logic of each of said divided hardware units in said digital circuit as a complete device by said hardware description language simulation means from said functional models, said structural models and language models, (ii) at the stage of a mixed level at which said digital circuit is expressed as a mixed state of said functional models and said structural models; and a fifth step of verifying the logic of said hardware units in said digital circuit as a complete device by said hardware description language simulation means from said structural models and said language models, (iii) at the stage of the structural level at which said digital circuit is expressed by only said structural models.

Claim 23

A digital circuit design assist method using a plurality of digital circuit design assist systems for designing a desired digital circuit consisting of a plurality of hardware units for controlling said digital circuit as a unit, said method comprising: a first step of generating each of functional models from each of a plurality of previously divided circuit units; a second step of verifying the logic of said hardware units in said digital circuit as a complete device by hardware description language simulation means from functional models and from language models individually expressing a plurality of components constituting each of said hardware units by a hardware description language, (i) at a functional level stage where only said functional models functionally express said digital circuit in said hardware description language; a third step of generating each of structural models having the same logic as that of the corresponding functional models by using any one of logic synthesis means for converting said functional models to said structural models structurally expressed by said hardware description language, coding generation means for generating new structural models through a text editor by coding input, and graphic generation means for generating new structural models through a block editor for expressing each of said components by an inherent symbol, drawing and arranging said symbols on a screen, drawing wires between said components arranged and image-processing them; a fourth step of executing verification of the logic of each of said divided hardware units in said digital circuit as a complete device by said hardware description language simulation means from said functional models, said structural models and language models, (ii) at the stage of a mixed level at which said digital circuit is expressed as a mixed state of said functional models and said structural models; and a fifth step of verifying the logic of said hardware units in said digital circuit as a complete device by said hardware description language simulation means from said structural models and said language models, (iii) at the stage of the structural level at which said digital circuit is expressed by only said structural models.

Claim 24

A digital circuit design assist method using a plurality of digital circuit design assist systems for designing a desired digital circuit consisting of a plurality of hardware units for controlling said digital circuit as a unit, said method comprising: a first step of down-loading software comprising at least one of said firmware, an application program loaded in a storage unit of said digital circuit, for executing a predetermined processing, and a diagnostic program for verifying the logic at least a part of said digital circuit, to said hardware description language simulation means through a software program code interface; a second step of verifying the logic of said hardware units in said digital circuit as one complete digital circuit by said hardware description language simulation means from said functional models, a language models expressing individually a plurality of components constituting each of said hardware units by said hardware description language and said software, and verifying the logic of said software independently from the verification of the logic of said hardware units, (i) at the stage of the functional level at which said digital circuit is expressed by only said functional models functionally expressing each of said divided digital circuits by said hardware description language; a third step of generating said structural models by the use of at least one logic synthesis means for converting said functional models to said structural models structurally expressed by said hardware description language, coding generation means for generating new structural models through a text editor by coding input and graphic generation means for generating new structural models through a block editor for expressing each of said components by an inherent symbol, drawing and arranging said symbols on a screen, drawing wiring between said components and image-processing them; a fourth step of verifying the logic of said hardware units in said digital circuit as one complete digital circuit by said hardware description language simulation means from said functional models, said structural models, said language models and said software, and verifying the logic of said software independently from the verification of the logic of said hardware unit, (ii) at the stage of a mixed level where said digital circuit is expressed by said functional models and said structural models in a mixed state; and a fifth step of verifying the logic of said hardware units in said circuit as one complete digital circuit by said hardware description language simulation means from said structural models, said language models and said software, and verifying the logic from said software independently from the verification of the logic of said hardware units, (iii) at the stage of a structural level where said digital circuit is expressed by only said structural models.

Claim 25

A digital circuit design assist method using a plurality of digital circuit design assist systems for designing a desired digital circuit consisting of a plurality of hardware units for controlling said digital circuit as a unit, said method comprising: a first step of down-loading software comprising at least one of said firmware, an application program loaded in a storage unit of said digital circuit, for executing a predetermined processing, and a diagnostic program for verifying the logic at least a part of said digital circuit, to said hardware description language simulation means through a software program code interface; a second step of verifying the logic of said hardware units in said digital circuit as one complete digital circuit by said hardware description language simulation means from said functional models, a language models expressing individually a plurality of components constituting each of said hardware units by said hardware description language and said software, and verifying the logic of said software independently from the verification of the logic of said hardware units, (i) at the stage of the functional level at which said digital circuit is expressed by only said functional models functionally expressing each of said divided digital circuits by said hardware description language; a third step of generating said structural models by the use of at least one logic synthesis means for converting said functional models to said structural models structurally expressed by said hardware description language, coding generation means for generating new structural models through a text editor by coding input and graphic generation means for generating new structural models through a block editor for expressing each of said components by an inherent symbol, drawing and arranging said symbols on a screen, drawing wiring between said components and image-processing them; a fourth step of verifying the logic of said hardware units in said digital circuit as one complete digital circuit by said hardware description language simulation means from said functional models, said structural models, said language models and said software, and verifying the logic of said software independently from the verification of the logic of said hardware unit, (ii) at the stage of a mixed level where said digital circuit is expressed by said functional models and said structural models in a mixed state; and a fifth step of verifying the logic of said hardware units in said circuit as one complete digital circuit by said hardware description language simulation means from said structural models, said language models and said software, and verifying the logic from said software independently from the verification of the logic of said hardware units, (iii) at the stage of a structural level where said digital circuit is expressed by only said structural models.

Claim 26

A digital circuit design assist method using a plurality of digital circuit design assist systems for designing a desired digital circuit consisting of a plurality of hardware units for controlling said digital circuit as a unit, said method comprising: a first step of creating a functional model functionally expressing a plurality of said divided digital circuits by a hardware description language; a second step of verifying the logic of said functional models by hardware description language simulation means and simultaneously executing substitution of said functional models to corresponding structural models without waiting for the verification of said logic, until creation of said functional models are completed; and a third step of independently executing automatic generation of layout for arranging said structural models in a physical space in said digital circuit, for example, on a printed board or on an integrated circuit by an automatic placing and routing tool on the basis of the dimensions of components expressed by said structural model and the amount of wiring, and verification of the logic of said hardware units.

Claim 27

A digital circuit design assist method using a plurality of digital circuit design assist systems for designing a desired digital circuit consisting of a plurality of hardware units for controlling said digital circuit as a unit, said method comprising: a first step of creating a functional model functionally expressing a plurality of said divided digital circuits by a hardware description language; a second step of verifying the logic of said functional models by hardware description language simulation means and simultaneously executing substitution of said functional models to corresponding structural models without waiting for the verification of said logic, until creation of said functional models are completed; and a third step of independently executing automatic generation of layout for arranging said structural models in a physical space in said digital circuit, for example, on a printed board or on an integrated circuit by an automatic placing and routing tool on the basis of the dimensions of components expressed by said structural model and the amount of wiring, and verification of the logic of said hardware units.