High density dynamic random access memory cell structure having a polysilicon pillar capacitor

Claim 1

A method for fabricating stacked storage capacitors on a semiconductor substrate, comprising the steps of: providing a semiconductor substrate having field oxide areas surrounded and electrically isolated device areas, said device areas having semiconductor devices formed, in part, from a patterned first polysilicon layer, and said devices areas having device contact areas; depositing a first insulating layer on said substrate and over said patterned first polysilicon layer, depositing a second insulating layer on said first insulating layer; anisotropically etching node contact openings in said second and first insulating layers to said device contact areas, thereby forming node contact openings having essentially vertical sidewalls for stacked storage capacitor bottom electrodes; depositing a conformal second polysilicon layer, and thereby filling said node contact openings, and also forming a uniformly thick second polysilicon layer elsewhere on said second insulating layer; oxidizing by thermal oxidation said second poly-silicon layer to said second insulating layer, and thereby leaving unoxidized polysilicon pillars in said node contact openings having essentially vertical sidewalls; isotropically etching said oxidized portion of said second polysilicon layer, and by said same isotropic etch, etching selectively said second insulating layer to said first insulating layer leaving free standing polysilicon pillars and thereby forming pillar-shaped bottom electrodes; forming a capacitor interelectrode dielectric layer on said bottom electrodes, and depositing and patterning a third polysilicon layer, and completing said stacked storage capacitors.

Claim 2

A method for fabricating stacked storage capacitors on a semiconductor substrate, comprising the steps of: providing a semiconductor substrate having field oxide areas surrounded and electrically isolated device areas, said device areas having semiconductor devices formed, in part, from a patterned first polysilicon layer, and said devices areas having device contact areas; depositing a first insulating layer on said substrate and over said patterned first polysilicon layer, depositing a second insulating layer on said first insulating layer; anisotropically etching node contact openings in said second and first insulating layers to said device contact areas, thereby forming node contact openings having essentially vertical sidewalls for stacked storage capacitor bottom electrodes; depositing a conformal second polysilicon layer, and thereby filling said node contact openings, and also forming a uniformly thick second polysilicon layer elsewhere on said second insulating layer; oxidizing by thermal oxidation said second poly-silicon layer to said second insulating layer, and thereby leaving unoxidized polysilicon pillars in said node contact openings having essentially vertical sidewalls; isotropically etching said oxidized portion of said second polysilicon layer, and by said same isotropic etch, etching selectively said second insulating layer to said first insulating layer leaving free standing polysilicon pillars and thereby forming pillar-shaped bottom electrodes; forming a capacitor interelectrode dielectric layer on said bottom electrodes, and depositing and patterning a third polysilicon layer, and completing said stacked storage capacitors.

Claim 12

A method for fabricating an array of dynamic random access memory (DRAM) cells on a semiconductor substrate, comprising the step of: forming on said semiconductor substrate an array device areas, surrounded and electrically isolated by field oxide areas; depositing and patterning a first polysilicon layer forming gate electrodes for field effect transistors in said device areas and forming word lines elsewhere on said substrate; and forming lightly doped source/drain areas in said device areas adjacent to said gate electrodes; forming sidewall spacers on said gate electrodes; and forming stacked storage capacitors contacting one of source/drain areas of each said field effect transistor in said array of device areas by; depositing a first insulating layer on said substrate and over said patterned first polysilicon layer, depositing a second insulating layer on said first insulating layer, anisotropically etching node contact openings in said second and first insulating layers to said device contact areas, thereby forming node contact openings having essentially vertical sidewalls for stacked storage capacitor bottom electrodes, depositing a conformal second polysilicon layer, and thereby filling said node contact openings, and also forming a uniformly thick second polysilicon layer elsewhere on said second insulating layer, oxidizing by thermal oxidation said second polysilicon layer to said second insulating layer, and thereby leaving unoxidized polysilicon pillars in said node contact openings having essentially vertical sidewalls, isotropically etching said oxidized portion of said second polysilicon layer, and by said same isotropic etch, etching selectively said second insulating layer to said first insulating layer leaving free standing polysilicon pillars and thereby forming pillar-shaped bottom electrodes, forming a capacitor interelectrode dielectric layer on said bottom electrodes, and depositing and patterning a third polysilicon layer, and forming the top electrodes for said stacked storage capacitors, depositing a third insulating layer, forming bit line contact openings in said third insulating layer and said first insulating layer to the other one of said source/drain contact areas of each said field effect transistor in said device areas; depositing and patterning a conducting layer and forming an array of bit lines on said third insulating layer and in said bit line contact openings, and thereby completing said dynamic random access memory (DRAM) device having an array of memory cells.

Claim 13

A method for fabricating an array of dynamic random access memory (DRAM) cells on a semiconductor substrate, comprising the step of: forming on said semiconductor substrate an array device areas, surrounded and electrically isolated by field oxide areas; depositing and patterning a first polysilicon layer forming gate electrodes for field effect transistors in said device areas and forming word lines elsewhere on said substrate; and forming lightly doped source/drain areas in said device areas adjacent to said gate electrodes; forming sidewall spacers on said gate electrodes; and forming stacked storage capacitors contacting one of source/drain areas of each said field effect transistor in said array of device areas by; depositing a first insulating layer on said substrate and over said patterned first polysilicon layer, depositing a second insulating layer on said first insulating layer, anisotropically etching node contact openings in said second and first insulating layers to said device contact areas, thereby forming node contact openings having essentially vertical sidewalls for stacked storage capacitor bottom electrodes, depositing a conformal second polysilicon layer, and thereby filling said node contact openings, and also forming a uniformly thick second polysilicon layer elsewhere on said second insulating layer, oxidizing by thermal oxidation said second polysilicon layer to said second insulating layer, and thereby leaving unoxidized polysilicon pillars in said node contact openings having essentially vertical sidewalls, isotropically etching said oxidized portion of said second polysilicon layer, and by said same isotropic etch, etching selectively said second insulating layer to said first insulating layer leaving free standing polysilicon pillars and thereby forming pillar-shaped bottom electrodes, forming a capacitor interelectrode dielectric layer on said bottom electrodes, and depositing and patterning a third polysilicon layer, and forming the top electrodes for said stacked storage capacitors, depositing a third insulating layer, forming bit line contact openings in said third insulating layer and said first insulating layer to the other one of said source/drain contact areas of each said field effect transistor in said device areas; depositing and patterning a conducting layer and forming an array of bit lines on said third insulating layer and in said bit line contact openings, and thereby completing said dynamic random access memory (DRAM) device having an array of memory cells.