US5284787A
Expired / Lapsed
US
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Method of making a semiconductor memory device having improved electrical characteristics
Assignee: Samsung Electronics Co Ltd
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Filing: 1991-12-31
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Granted: 1994-02-08
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Expires: 2011-12-31
Abstract
Abstract A semiconductor memory device and the method therefor is disclosed, in which memory cells having a transistor that has a source, a drain and a gate electrode, and a capacitor that has a storage electrode electrically connected to the source of the transistor, a dielectric layer and a plate electrode are formed on a semiconductor substrate in an orderly shape. In the memory cell, a covering layer is formed over the entire semiconductor region, except for an area defined to form the storage electrode, so as to be both insulated from the lower structure and the storage electrode. Accordingly, not only is prevented the phenomenon that data stored in a cell capacitor is destroyed by the residue of a polycrystal silicon layer, but also the surface thereof can be flattened in advance, limited only by the thickness of the polycrystal silicon layer.
Inventors
- 👤 Ji-hong Ahn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:23
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/0335; H10B12/30; H10B12/31; H10B12/318; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/042
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
241 words
A method for manufacturing a memory device in which memory cells each comprising a transistor having a gate electrode, a drain and a source electrically connected to a capacitor having a storage electrode, a dielectric layer and a plate electrode, are formed on a semiconductor substrate in an orderly shape, comprising the steps of: stacking an etch blocking layer, stacking a first polycrystal silicon layer and then stacking an insulating layer whose surface is planarized, over the entire surface of said semiconductor substrate on which said transistor is formed; forming a photosensitive film pattern for forming said storage electrode on said insulating layer; patterning said insulating layer and said first polycrystal silicon layer by using said photosensitive film pattern as a mask; forming a spacer layer over the entire surface of the resultant substrate; forming a spacer over the sidewalls of said patterned first polycrystal silicon layer and said insulating layer by etching said spacer layer; forming a second polycrystal silicon layer over the entire surface of said semiconductor substrate on which said spacer is formed; completing a storage electrode by partially etching said second polycrystal silicon layer to isolate each cell unit; removing at least a portion of said patterned insulating layer and said spacer by etching; forming a dielectric layer over the entire surface of the resultant semiconductor substrate; and forming a third polycrystal silicon layer over the entire surface of said dielectric layer, thereby, forming a plate electrode.
Claim 2
Independent Claim
241 words
A method for manufacturing a memory device in which memory cells each comprising a transistor having a gate electrode, a drain and a source electrically connected to a capacitor having a storage electrode, a dielectric layer and a plate electrode, are formed on a semiconductor substrate in an orderly shape, comprising the steps of: stacking an etch blocking layer, stacking a first polycrystal silicon layer and then stacking an insulating layer whose surface is planarized, over the entire surface of said semiconductor substrate on which said transistor is formed; forming a photosensitive film pattern for forming said storage electrode on said insulating layer; patterning said insulating layer and said first polycrystal silicon layer by using said photosensitive film pattern as a mask; forming a spacer layer over the entire surface of the resultant substrate; forming a spacer over the sidewalls of said patterned first polycrystal silicon layer and said insulating layer by etching said spacer layer; forming a second polycrystal silicon layer over the entire surface of said semiconductor substrate on which said spacer is formed; completing a storage electrode by partially etching said second polycrystal silicon layer to isolate each cell unit; removing at least a portion of said patterned insulating layer and said spacer by etching; forming a dielectric layer over the entire surface of the resultant semiconductor substrate; and forming a third polycrystal silicon layer over the entire surface of said dielectric layer, thereby, forming a plate electrode.
Claim 3
Dependent Claim
39 words
A method for manufacturing a semiconductor memory device according to claim 1, wherein said etch blocking layer in wet etching is formed of a material which has a different etch rate from that of the material forming said spacer.
Claim 4
Dependent Claim
20 words
A method for manufacturing a semiconductor memory device according to claim 2, wherein said etch blocking layer is a nitride.
Claim 5
Dependent Claim
28 words
A method for manufacturing a semiconductor memory device according to claim 1, wherein said first polycrystal silicon layer is a material which is not doped with an impurity.
Claim 6
Dependent Claim
26 words
A method for manufacturing a semiconductor memory device according to claim 1, wherein said first polycrystal silicon layer is a material into which impurity is doped.
Claim 7
Dependent Claim
25 words
A method for manufacturing a semiconductor memory device according to claim 5, wherein said first polycrystal silicon layer is electrically connected with said plate electrode.
Claim 8
Dependent Claim
22 words
A method for manufacturing a semiconductor memory device according to claim 5, wherein said first polycrystal silicon layer is connected to ground.
Claim 9
Dependent Claim
46 words
A method for manufacturing a semiconductor memory device according to claim 1, wherein said step of removing at least a portion of said patterned insulating layer and said spacer by etching consists of removing all of said patterned insulating layer and said spacer using wet etching.
Claim 10
Dependent Claim
21 words
A method for manufacturing a semiconductor memory device according to claim 8, wherein said insulating layer is either TEOS or BPSG.
Claim 11
Dependent Claim
39 words
A method for manufacturing a semiconductor memory device according to claim 8, wherein said spacer has a different etch rate for dry etching from that of said insulating layer, and the same or similar etch rates for wet etching.
Claim 12
Dependent Claim
67 words
A method for manufacturing a semiconductor memory device according to claim 1, wherein said step of removing at least a portion of said patterned insulating layer and said spacer consists of removing a portion of said patterned insulating layer and said spacer by dry etching, thereby, leaving a portion of said patterned insulating layer and said spacer on the top and sidewall of said first polysilicon layer.
Claim 13
Dependent Claim
26 words
A method for manufacturing a semiconductor memory device according to claim 11 wherein said insulating layer and said spacer are removed at the same etching rate.
Claim 14
Dependent Claim
88 words
A method for manufacturing a semiconductor memory device according to claim 1, wherein said step of completing a storage electrode by partially etching said second polycrystal silicon layer to isolate each cell unit comprises the steps of applying a first material over the entire surface of said semiconductor substrate on which said second polycrystal silicon layer is formed; etching back said first material until upper portions of the curved surface of said second polycrystal silicon layer become exposed; and etching the exposed portion of said polycrystal silicon layer.
Claim 15
Dependent Claim
33 words
A method for manufacturing a semiconductor memory device according to claim 13, wherein said first material has a different etch late from those of said insulating layer and said spacer for dry etching.
Claim 16
Dependent Claim
19 words
A method for manufacturing a semiconductor memory device according to claim 14, wherein said first material is a photoresist.
Claim 17
Independent Claim
282 words
A method for manufacturing a semiconductor memory device in which memory cells each comprising a transistor having a gate electrode, a drain and a source electrically connected a capacitor having a storage electrode, a dielectric layer and a plate electrode, are formed on a semiconductor substrate in an orderly shape, said method comprising the steps of: stacking an etch blocking layer, stacking a first polycrystal silicon layer, stacking an first insulating layer and then second insulating layer whose surface is flattened, over the entire surface of said semiconductor substrate; forming a photosensitive film pattern for forming said storage electrode on said second insulating layer; patterning said first and second insulating layer and first polycrystal silicon layer by using said photosensitive film pattern as a mask; forming a spacer layer over the entire surface of the resultant substrate; forming a spacer over the sidewalls of said patterned first polycrystal silicon layer and said first and second insulating layer, by etching said spacer layer; forming a second polycrystal silicon layer over the entire surface of said semiconductor substrate on which said spacer is formed; completing a storage electrode by partially etching said second polycrystal silicon layer to isolate each cell unit; removing a portion of said spacer formed on the sidewall of said second insulating layer and said second insulating layer, by etching at the same etching late; removing the remainder portion of said spacer formed on the sidewall of said first insulating layer and said first insulating layer by etching; forming a dielectric film over the entire surface of the resultant semiconductor substrate; and forming a third polycrystal silicon layer over the entire surface of said dielectric film, thereby forming a plate electrode.
Claim 18
Independent Claim
282 words
A method for manufacturing a semiconductor memory device in which memory cells each comprising a transistor having a gate electrode, a drain and a source electrically connected a capacitor having a storage electrode, a dielectric layer and a plate electrode, are formed on a semiconductor substrate in an orderly shape, said method comprising the steps of: stacking an etch blocking layer, stacking a first polycrystal silicon layer, stacking an first insulating layer and then second insulating layer whose surface is flattened, over the entire surface of said semiconductor substrate; forming a photosensitive film pattern for forming said storage electrode on said second insulating layer; patterning said first and second insulating layer and first polycrystal silicon layer by using said photosensitive film pattern as a mask; forming a spacer layer over the entire surface of the resultant substrate; forming a spacer over the sidewalls of said patterned first polycrystal silicon layer and said first and second insulating layer, by etching said spacer layer; forming a second polycrystal silicon layer over the entire surface of said semiconductor substrate on which said spacer is formed; completing a storage electrode by partially etching said second polycrystal silicon layer to isolate each cell unit; removing a portion of said spacer formed on the sidewall of said second insulating layer and said second insulating layer, by etching at the same etching late; removing the remainder portion of said spacer formed on the sidewall of said first insulating layer and said first insulating layer by etching; forming a dielectric film over the entire surface of the resultant semiconductor substrate; and forming a third polycrystal silicon layer over the entire surface of said dielectric film, thereby forming a plate electrode.
Claim 19
Dependent Claim
29 words
A method for manufacturing a semiconductor memory device according to claim 16, wherein said spacer, said first insulating layer and said second insulating layer are removed by dry etching.
Claim 20
Dependent Claim
40 words
A method for manufacturing a semiconductor memory device according to claim 17, wherein said first insulating layer is different in its etching late for dry etching from said second insulating layer and the inter-insulating layer formed to isolate said transistor.
Claim 21
Dependent Claim
30 words
A method for manufacturing semiconductor memory device according to claim 18, wherein the etching rate of said first insulating layer is greater than the etching rate of said inter-insulating layer.
Claim 22
Independent Claim
229 words
A method for manufacturing a memory device in which memory cells each comprising a transistor having a gate electrode, a drain and a source electrically connected to a capacitor having a storage electrode, a dielectric layer and a plate electrode, are formed on a semiconductor substrate in an orderly shape, said method comprising the steps of: Stacking etch blocking layer, stacking a first polycrystal silicon layer, and then stacking an insulating layer whose surface is flattened, over the entire surface of said semiconductor substrate; forming a photosensitive film pattern for forming said storage electrode on said insulating layer; patterning said insulating layer and first polycrystal silicon by using said photosensitive film pattern as a mask; forming an oxide layer by oxidizing the sidewall of said patterned first polycrystal silicon layer; forming a contact hole on said source of said transistor; forming a second polycrystal silicon layer over the entire surface of said semiconductor substrate on which said contact hole is formed; completing a storage electrode by partially etching said second polycrystal silicon layer to isolate each cell unit; removing said insulating layer and said oxide layer formed on the sidewall of said first polycrystal silicon layer; forming a dielectric film over the entire surface of the resultant semiconductor substrate; and forming a thud polycrystal silicon layer over the entire surface of said dielectric film, thereby forming said plate electrode.
Claim 23
Independent Claim
229 words
A method for manufacturing a memory device in which memory cells each comprising a transistor having a gate electrode, a drain and a source electrically connected to a capacitor having a storage electrode, a dielectric layer and a plate electrode, are formed on a semiconductor substrate in an orderly shape, said method comprising the steps of: Stacking etch blocking layer, stacking a first polycrystal silicon layer, and then stacking an insulating layer whose surface is flattened, over the entire surface of said semiconductor substrate; forming a photosensitive film pattern for forming said storage electrode on said insulating layer; patterning said insulating layer and first polycrystal silicon by using said photosensitive film pattern as a mask; forming an oxide layer by oxidizing the sidewall of said patterned first polycrystal silicon layer; forming a contact hole on said source of said transistor; forming a second polycrystal silicon layer over the entire surface of said semiconductor substrate on which said contact hole is formed; completing a storage electrode by partially etching said second polycrystal silicon layer to isolate each cell unit; removing said insulating layer and said oxide layer formed on the sidewall of said first polycrystal silicon layer; forming a dielectric film over the entire surface of the resultant semiconductor substrate; and forming a thud polycrystal silicon layer over the entire surface of said dielectric film, thereby forming said plate electrode.
Claim 24
Dependent Claim
25 words
A method for manufacturing a semiconductor memory device according to claim 20, wherein said contact hole is formed by self alignment without any masking process.
Claim 25
Dependent Claim
31 words
A method for manufacturing a semiconductor memory device according to claim 20, wherein said insulating layer and said oxide layer have the same or a similar etch rates for wet etching.
Claim 26
Dependent Claim
25 words
A method for manufacturing a semiconductor memory device according to claim 20, wherein said oxide layer and said insulating layer is removed by wet etching.
Claim 27
Dependent Claim
37 words
A method for manufacturing a semiconductor memory device according to claim 20, wherein said insulating layer is composed of a first and second insulating layers having etching rate that are different from each other for dry etching.
Claim 28
Dependent Claim
36 words
A method for manufacturing a semiconductor memory device according to claim 24, wherein said first insulating layer has an etching rate that is different from the inter-insulating layer formed to isolate said transistor for dry etching.
Claim 29
Dependent Claim
24 words
A method for manufacturing a semiconductor memory device according to claim 25, wherein said first insulating layer is etched faster than said inter-insulating layer.
Claim 30
Dependent Claim
27 words
A method for manufacturing a semiconductor memory device according to claim 20, wherein both said oxide layer and said insulating layer are partially removed by dry etching.
References Cited (Backward Citations)
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