Stacked v-cell capacitor using a disposable composite dielectric on top of a digit line

Claim 1

A process for fabricating a DRAM array on a silicon substrate, said process comprising the following sequence of steps: creating a plurality of separately isolated active areas arranged in parallel interdigitated rows and parallel non-interdigitated columns; creating a gate dielectric layer on top of each active area; depositing a first conductive layer superjacent surface of said array; depositing a first dielectric layer superjacent said first conductive layer; masking and etching said first conductive and said first dielectric layers to form a plurality of parallel conductive word lines aligned along said rows such that each said word line passes over a inner portion of each said active area being separated therefrom by a remnant of said gate dielectric layer; creating a conductively-doped digit line junction and storage node junction within each said active area on opposite sides of each said word line; depositing a second dielectric layer superjacent said array surface; creating a first self-aligned buried contact location at each said digit line junction in each said active area; depositing a second conductive layer superjacent said array surface, said second conductive layer making direct contact to said digit line junctions at said first buried contact locations; depositing a third dielectric layer superjacent to said second conductive layer; depositing a fourth dielectric layer superjacent to said third dielectric layer; masking and etching said second conductive layer and said third and said fourth dielectric layers to form a plurality of parallel conductive digit lines aligned along said columns such that a digit line makes electrical contact at each digit line junction within a column, said digit lines running perpendicular to and over said word lines forming a 3-dimensional, waveform-like topology; depositing a fifth dielectric layer superjacent said array surface; etching said fifth dielectric layer to form vertical spacers adjacent said digit lines and said third and said fourth dielectrics; creating a second self-aligned buried contact location at each said storage node junction in each said active area; depositing a third conductive layer superjacent said array surface assuming said waveform-like topology in response to existing topology, said third conductive layer making contact to said storage node junctions at said second buried contact locations; etching said fourth dielectric layer; patterning said third conductive layer to form a storage node plate at each said storage node junction, said storage node plate having a v-shaped cross-section; etching said vertical spacers in a vertical direction; depositing a cell dielectric layer adjacent and coextensive with said storage node plate and adjacent said array surface; and depositing a fourth conductive layer adjacent to and coextensive with said cell dielectric layer to form a cell plate common to the entire memory array.