US5594877A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for transferring data onto buses having different widths
Assignee: Samsung Electronics Co Ltd
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Filing: 1994-10-05
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Granted: 1997-01-14
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Expires: 2014-10-05
Abstract
Abstract The present invention provides a memory system interface design, which provides access to a dual width memory bus. Specifically, a subsystem and method provides for interfacing with a 32 bit or a 64 bit bus. The 32 bit bus would be used for low end products, and the 64 bit bus would be used for high end products. A memory control unit (MCU) supports both the 32 bit and 64 bit modes. The use of a 32 bit or 64 bit memory subsystem gives a user more room to adjust system cost and performance.
Inventors
- 👤 Derek J. Lentz
- 👤 Cheng-Long Tang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-10 01:28
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/18; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0855; G06F13/38; G06F13/40; G06F13/4004; G06F13/4009; G06F13/4018
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
276 words
A system that provides access to a plurality of different width buses in a computer-based system, said system configured to efficiently transfer data between a memory and one or more bus requestors over a bus coupled to said computer-based system, said system comprising: (a) means for determining the width of the bus currently coupled to the computer-based system; (b) selecting means for transferring data between the bus requestor and temporary storage buffers wherein said selecting means comprises a plurality of multiplexers with an interface to said temporary storage buffers configured to select blocks of said data corresponding to said determined width; (c) storage means for receiving and storing in said temporary storage buffers said selected blocks of data to be outputted in blocks corresponding to said determined width; and (d) a selection unit configured to select bytes of data from each said selected block of data that have been modified by the bus requestor for transfer to the memory, said selection unit includes a plurality of multiplexers each having only two data inputs, a first data input and a second data input, wherein said first data input is connected to a byte of data of said selected block of data originally read from the memory before modification by the bus requestor and said second data input is connected to a byte of data of said selected block of data modified by the bus requestor, said first data input is selected if said byte of data of said selected block of data has not been modified and said second data input is selected if said byte of data of said selected block of data has been modified.
Claim 2
Independent Claim
276 words
A system that provides access to a plurality of different width buses in a computer-based system, said system configured to efficiently transfer data between a memory and one or more bus requestors over a bus coupled to said computer-based system, said system comprising: (a) means for determining the width of the bus currently coupled to the computer-based system; (b) selecting means for transferring data between the bus requestor and temporary storage buffers wherein said selecting means comprises a plurality of multiplexers with an interface to said temporary storage buffers configured to select blocks of said data corresponding to said determined width; (c) storage means for receiving and storing in said temporary storage buffers said selected blocks of data to be outputted in blocks corresponding to said determined width; and (d) a selection unit configured to select bytes of data from each said selected block of data that have been modified by the bus requestor for transfer to the memory, said selection unit includes a plurality of multiplexers each having only two data inputs, a first data input and a second data input, wherein said first data input is connected to a byte of data of said selected block of data originally read from the memory before modification by the bus requestor and said second data input is connected to a byte of data of said selected block of data modified by the bus requestor, said first data input is selected if said byte of data of said selected block of data has not been modified and said second data input is selected if said byte of data of said selected block of data has been modified.
Claim 3
Dependent Claim
15 words
The system of claim 1, wherein said modified data is modified during a read-modify-write operation.
Claim 4
Dependent Claim
18 words
The system of claim 1, wherein said data is transferred onto the bus using a double pumping scheme.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-14 | 2000-07-15 | 2001-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-14 | 2004-07-15 | 2005-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-14 | 2008-07-15 | 2009-01-14 | $7700.00 | Window Closed / Lapsed |