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JPS649561A Expired / Lapsed JP ⏱️ 0.0 years remaining

Computer

Assignee: Seiko Epson Corp
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Filing: 1987-07-02
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Granted: —
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Expires: 2007-07-02
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Abstract

Abstract PURPOSE:To provide complete interchangeability on a software by checking the data width on a data bus so as to control the data processing speed of a CPU depending on the size, thereby operating the computer system having the same internal data processing unit but using CPUs with different data bus width timewise entirely identically. CONSTITUTION:The titled computer is provided with a storage element 2 storing information such as a program, a CPU 1, a data bus 6 giving/receiving a data with the element 2, a word data detecting circuit 7 checking the data width on the data bus 6, and a speed control circuit 8 controlling the processing speed of the CPU 1 depending on the signal generated from the word data detecting circuit 7. Thus, the CPU having the same data processing unit but different data bus width is operated at any time in the same timing to provide the complete interchangeable to the software.

Inventors

  • 👤 Noriyoshi Otsuki

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-10 02:35
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4009; G06F13/4018

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